Methods and apparatus for facilitating physical synthesis of an integrated circuit design
AssigneeFulcrum Microsystems, Inc.
InventorsPeter Beerel, Andrew Lines, Qing Wu
Life of this patent
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Abstract
Methods and apparatus are described for facilitating physical synthesis of an integrated circuit design. A set of paths between observable nodes in a netlist representing the circuit design is generated. Each path corresponds to a sequence of signal transitions. Transistors represented in the netlist are sized to attempt to meet a delay constraint for each path. The delay constraint corresponds to a unit delay times the number of signal transitions in the corresponding path. A plurality of individual delays of different durations are allocated among the transitions for at least one of the paths to meet the delay constraint. At least one of the individual delays exceeds the unit delay.
Claims99
A computer-implemented method for facilitating physical synthesis of an integrated circuit design, the method comprising:
- generating a set of paths between observable nodes in a netlist representing the circuit design, each path corresponding to a sequence of signal transitions;
- and
- sizing transistors represented in the netlist to attempt to meet a delay constraint for each path, the delay constraint corresponding to an average unit delay times the number of signal transitions in the corresponding path, a plurality of individual delays of different durations being allocated among the transitions for at least one of the paths to meet the delay constraint, at least one of the individual delays exceeding the average unit delay.
A computer-implemented method for facilitating physical synthesis of integrated circuit designs, the method comprising:
- generating a netlist representing an asynchronous circuit design characterized by transmission of signals according to an asynchronous handshake protocol;
- generating a set of paths between observable nodes in the netlist, each path having a first number of signal transitions;
- and
- sizing transistors represented in the netliut to attempt to meet a delay constraint for each path, the delay constraint corresponding to an average unit delay times the first number, a plurality of individual delays of different durations being allocated among the transitions for at least one of the paths to meet the delay constraint, at least one of the individual delays exceeding the average unit delay.
A computer-implemented method for facilitating physical synthesis of integrated circuit designs, the method comprising:
- generating a netlist representing an asynchronous circuit design characterized by transmission of signals according to an asynchronous handshake protocol;
- generating a set of paths from the netlist, each path corresponding to a sequence of nodes each having upward and downward signal transitions associated therewith;
- for each of selected nodes, representing the corresponding upward transition by a pull up half operator and the corresponding downward transition by a pull down half operator and
- sizing transistors represented in the netlist to attempt to meet a delay constraint for each path, first selected transistors associated with the pull up half operator for each selected node being sized independently from second selected transistors associated with the corresponding pull down half operator.
Dependencies are inferred from the claim text.