US 6,785,874 B2Granted

Layout verification method, program thereof, and layout verification apparatus

AssigneeRenesas Technology Corp.

InventorEiji Tsukuda

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Abstract

Provided are a layout verification apparatus and a layout verification method, each employing an L/S matrix to achieve higher accuracy of verification, as well as a program thereof. The layout verification method is realized by dividing each segment in accordance with the layout of its surrounding other polygon. For instance, in FIG. 3, since the left side of polygon (P1) (i.e., segment Segc) is, over its entire segment length, most adjacent to polygon (P5), this side is not divided. Since the upper side of the polygon (P1) is, only in part of its segment length, most adjacent to polygon (P7) within distance (R), this side is divided into segment (Segb1) that corresponds to the part adjacent to the polygon (P7), and segment (Segb2) that is the rest. Then, the L/S matrix is referred to segment by segment, to judge whether the polygon can be resolved.

Claims7

Dependent claims

A layout verification method using a layout data of a semiconductor integrated circuit,

said layout data containing plural polygons indicating wiring patterns,
said polygons being made up of plural segments that are sides,
said method comprising the steps of:
(a) dividing plural segments forming one of said plural polygons in said layout data, based on a predetermined rule defined beforehand relative to the layout of other surrounding polygon;
(b) with respect to said segments divided and segments not divided, detecting a width of wiring containing each of said segments and a width of space most adjacent to each of said segments;
(c) evaluating the possibility of resolution of each of said segments by referring to data of conditions under which resolution can be performed, in which a predetermined conditione relative to the possibility of resolution of said segments in a wafer process is stored in association with a combination of said width of wiring and said width of space;
and
(d) outputting an error information when there is a segment of which possibility of resolution is negative based on the result of evaluation in said step (c).

5 more elements

Dependencies are inferred from the claim text.