Method of optimizing high performance CMOS integrated circuit designs for power consumption and speed using global and greedy optimizations in combination

A method of optimizing speed and predicted power consumption of a design for an integrated circuit, the design for an integrated circuit comprising at least one path further comprising at least one gate, the method comprising the steps of:

• creating a machine representation of a parent state representing at least some devices of the integrated circuit design, where for each device in a path of the integrated circuit the parent state further comprises device size information;
• creating a population of individual states from at least one parent state;
• scoring individual states of the population for timing and power dissipation to create a score for each individual state;
• selecting survivor individual states of the population based upon their scores;
• iterating the steps of creating a population, scoring individual states, and selecting survivor individual states, where the survivor individual states of each iteration become parent states of the next iteration;
• determining, for at least one device of at least one survivor state, slopes of speed and power consumption as affected by device size;
• adjusting device sizes of at least one survivor state according to the determined slopes;
• and
• selecting a best individual survivor state as an optimized state and updating an integrated circuit netlist therefrom.