Semiconductor device capable of adjusting timing of input waveform by tester with high accuracy
AssigneeRenesas Technology Corp.
InventorMitsutaka Niiro
Life of this patent
Estimating the term…
Abstract
A timing adjusting circuit is mounted on a semiconductor device. A reference signal TREFIN and signals TPa to TPx to be adjusted are supplied from a tester via transmission lines on a test jig. By gradually advancing phases of the signals TPa to TPx with respect to a trigger signal TRIG generated on the basis of the reference signal, the differences of transition timings of driver waveforms are held in a plurality of registers corresponding to the transmission lines. The data held by the plurality of registers is sent to the tester via a storage result outputting circuit. On the basis of the data, output timings of the driver waveforms can be adjusted by the tester with high accuracy.
Claims10
A semiconductor device comprising:
- a reference terminal for receiving a reference signal;
- a plurality of terminals;
- a capturing circuit for capturing an input signal supplied to said plurality of terminals in accordance with said reference signal and temporarily holding the input signal;
- a data holding circuit for receiving the data held by said capturing circuit and holding data of an amount corresponding to a predetermined number of capturing times;
- and
- an output circuit for outputting the data held by said data holding circuit to the outside.
A semiconductor device testing method of testing a semiconductor device by a tester via a test jig, comprising the steps of:
- attaching a semiconductor device to said test jig, the semiconductor device having a reference terminal for receiving a reference signal, a plurality of terminals, and a data holding circuit for holding data corresponding to a time difference between said reference signal and an input signal supplied to said plurality of terminals;
- supplying said reference signal and said input signal from said tester and allowing said data holding circuit to hold delay amount data of each of a plurality of signal transmission lines of the test jig corresponding to said plurality of terminals;
- reading said delay amount data by said tester via said test jig;
- and
- correcting a timing of a signal which is outputted to said plurality of terminals by said tester in accordance with said delay amount data.
Dependencies are inferred from the claim text.