Fixed-logic signal generated in an integrated circuit for testing a function macro integrated in an integrated circuit
AssigneeFujitsu Limited
InventorKatsuya Ishikawa
Life of this patent
Estimating the term…
Abstract
A fixed-logic signal generated inside an integrated circuit is selectively supplied via selectors (Sm+1 to Sn) to input terminals (INm+1 to INn) of a function macro (1) for receiving signals whose logic levels are fixed to “H” or “L” on at least one test pattern. This eliminates any external input terminal for inputting such fixed-logic signal. When the integrated circuit includes function macros, they can be simultaneously tested with this construction.
Claims37
An integrated circuit test apparatus for testing a function macro integrated in an integrated circuit, wherein
- a fixed-logic signal generated inside said integrated circuit is selectively supplied to an input terminal of the function macro for receiving a signal whose logic is fixed on at least one test pattern.
An integrated circuit test apparatus for testing a function macro integrated in an integrated circuit, wherein
- a signal input from a specific external input terminal of said integrated circuit is selectively supplied to input terminals of the function macro for receiving signals of the same logic level on at least one test pattern.
An integrated circuit test apparatus for testing a function macro integrated in an integrated circuit, wherein
- to an input terminal of the function macro for receiving a signal opposite in logic level to one signal on at least one test pattern, the opposite logic signal is generated from said one signal inside said integrated circuit, and selectively supplied.
An integrated circuit test apparatus for testing a function macro integrated in an integrated circuit, wherein
- to an input terminal of the function macro for receiving a signal delayed from one signal by a predetermined amount or an opposite logic signal on at least one test pattern, the signal delayed by the predetermined amount or the opposite logic signal is generated from said one signal inside said integrated circuit, and selectively supplied.
An integrated circuit test apparatus for testing a function macro integrated in an integrated circuit, comprising:
- a signal generation circuit for generating a fixed-logic signal on at least one test pattern, or a signal having a specific relationship with a signal input from a specific external input terminal of said integrated circuit;
- and
- a selection circuit for selectively supplying the signal generated by said signal generation circuit to an input terminal of said function macro.
An integrated circuit test apparatus for testing a function macro integrated in an integrated circuit, wherein
- a test result is determined for each signal output from at least one output terminal of said function macro by comparing a fixed-logic signal output from an output terminal of said function macro on at least one test pattern with a fixed-logic expectation signal generated inside said integrated circuit, and determination results are summed up and selectively supplied to a specific external output terminal of said integrated circuit.
An integrated circuit test apparatus for testing a function macro integrated in an integrated circuit, wherein
- a test result is determined for each signal output from at least one output terminal of said function macro by comparing signals of the same logic level output from output terminals of said function macro on at least one test pattern with an expectation signal input from a specific external input terminal of said integrated circuit, and determination results are summed up and selectively supplied to a specific external output terminal of said integrated circuit.
An integrated circuit test apparatus for testing a function macro integrated in an integrated circuit, wherein
- an expectation signal opposite in logic level to one expectation signal on at least one test pattern is generated from said one expectation signal inside said integrated circuit, and
- a test result is determined for each signal output from at least one output terminal of said function macro by comparing a signal output from an output terminal of said function macro with said one expectation signal and said expectation signal opposite in logic level to said one expectation signal, and determination results are summed up and selectively supplied to a specific external output terminal of said integrated circuit.
An integrated circuit test apparatus for testing a function macro integrated in an integrated circuit, wherein
- an expectation signal delayed from one expectation signal by a predetermined amount or an expectation signal of opposite logic on at least one test pattern is generated from said one expectation signal inside said integrated circuit, and
- a test result is determined for each signal output from at least one output terminal of said function macro by comparing a signal output from an output terminal of said function macro with said one expectation signal and said expectation signal delayed from said one expectation signal by a predetermined amount or said expectation signal of opposite logic, and determination results are summed up and selectively supplied to a specific external output terminal of said integrated circuit.
An integrated circuit test apparatus for testing a function macro integrated in an integrated circuit, comprising:
- an internal determination circuit for comparing a signal output from an output terminal of said function macro with, as an expectation signal of a test, a fixed-logic signal or a signal having a specific relationship with a signal input from a specific external input terminal of said integrated circuit to determine a test result for each signal output from at least one output terminal of said function macro, summing up determination results, and selectively supplying the summed result to a specific external output terminal of said integrated circuit.
An integrated circuit test apparatus for testing a function macro integrated in an integrated circuit, comprising:
- a first selection circuit for selecting a fixed-logic signal generated inside the integrated circuit;
- a second selection circuit for selecting the selected fixed-logic signal and supplying to an input terminal of the function macro.
A test method for testing a function macro integrated in an integrated circuit, comprising:
- generating a fixed-logic signal inside in the integrated circuit;
- and
- supplying the fixed-logic signal to an input terminal of the function macro selectively as a signal, the fixed-logic signal having logic fixed on at least one test pattern.
A test method for testing a function macro integrated in an integrated circuit, comprising:
- receiving a signal from a specific external input terminal of said integrated circuit;
- and
- selectively supplying said signal to input terminals of the function macro for receiving signals of the same logic level on at least one test pattern.
A test method for testing a function macro integrated in an integrated circuit, comprising:
- generating an opposite logic signal inside said integrated circuit, the opposite logic signal opposite in logic level to one signal on at least one test pattern;
- and
- selectively applying said opposite logic signal to an input terminal of the function macro.
A test method for testing a function macro integrated in an integrated circuit, comprising:
- generating a test signal from one signal inside said integrated circuit, said test signal either being delayed from one said signal by a predetermined amount or being an opposite logic signal on at least one test pattern;
- and
- selectively supplying said test signal to an input terminal of said function macro.
A test method for testing a function macro integrated in an integrated circuit, comprising:
- generating either a fixed-logic signal on at least one test pattern, or a signal having a specific relationship with a signal input from a specific external input terminal of said integrated circuit;
- and
- selectively supplying the generated signal to an input terminal of said function macro.
A test method for testing a function macro integrated in an integrated circuit, comprising:
- determining a test result for each signal output from at least one output terminal of said function macro by comparing a fixed-logic signal output from an output terminal of said function macro on at least one test pattern with a fixed-logic expectation signal generated inside said integrated circuit;
- summing up determination results;
- and
- selectively supplying the summed determination results to a specific external output terminal of said integrated circuit.
A test method for testing a function macro integrated in an integrated circuit, comprising:
- determining a test result for each signal output from at least one output terminal of said function macro by comparing signals of the same logic level output from output terminals of said function macro on at least one test pattern with an expectation signal input from a specific external input terminal of said integrated circuit;
- summing up determination results;
- and
- selectively supplying the summed determination results to a specific external output terminal of said integrated circuit.
A test method for testing a function macro integrated in an integrated circuit, comprising:
- generating an expectation signal from one expectation signal inside said integrated circuit, said generated expectation signal opposite in logic level to said one expectation signal on at least one test pattern;
- determining a test result for each signal output from at least one output terminal of said function macro by comparing a signal output from an output terminal of said function macro with said one expectation signal and said generated expectation signal opposite in logic level to said one expectation signal;
- summing up determination results;
- and
- selectively supplying the summed determination results to a specific external output terminal of said integrated circuit.
A test method for testing a function macro integrated in an integrated circuit, comprising:
- generating an expectation signal from one expectation signal inside said integrated circuit, the generated expectation signal delayed from the one expectation signal by a predetermined amount or being an expectation signal of opposite logic on at least one test pattern;
- determining a test result for each signal output from at least one output terminal of said function macro by comparing a signal output from an output terminal of said function macro with said one expectation signal and said generated expectation signal;
- summing up determination results;
- and
- selectively supplying the summed determination results to a specific external output terminal of said integrated circuit.
A test method for testing a function macro integrated in an integrated circuit, comprising:
- comparing a signal output from an output terminal of said function macro with, as an expectation signal of a test, a fixed-logic signal or a signal having a specific relationship with a signal input from a specific external input terminal of said integrated circuit to determine a test result for each signal output from at least one output terminal of said function macro;
- summing up determination results;
- and
- selectively supplying the summed result to a specific external output terminal of said integrated circuit.
A test method for testing a function macro integrated in an integrated circuit, comprising:
- selecting a fixed-logic signal generated inside the integrated circuit;
- and
- supplying the selected fixed-logic signal to an input terminal of the function macro.
Dependencies are inferred from the claim text.