Implementation of an assertion check in ATPG models

Abstract

A system and method for implementing an assertion check in an ATPG scan cell is provided. The assertion check includes an error signal generator within a scan cell that generates an error signal when there is a violation of necessary conditions for testing the integrated circuit using APTG. According to the illustrative embodiment, the scan cell comprises a set-reset flip-flop paired with a latch. The flip-flop is used as a master storage element and the latch is used as a slave storage element to form a scan path. The master flip-flop and the slave latch are connected to form a shift register for shifting test data through the circuit under test. A system clock drives the standard operational mode of the storage elements and a shift clock drives the test mode. An enable clock is used to activate the system clock and switch the scan cell between the standard operational mode and the test mode. The assertion check ensures that the enable clock and the shift clock are not both high at the same time by generating an error signal at the output of the flip-flop when both clocks are simultaneously high. The assertion check is implemented by adding a logic gate or a set of logic gates to the scan cell and connecting the output of the logic gate to the set and reset pins of the flip-flop, such that the flip-flop generates an error signal when both clocks are high.

Dependencies are inferred from the claim text.