Test access port (TAP) controller system and method to debug internal intermediate scan test faults

An intermediate test access port (TAP) controller internal scan test system further comprising:

• a TAP output multiplexer (MUX) adapted to output one of its input signals as a test data out (TDO) signal;
• a TAP output control circuit coupled to said TAP output multiplexer, said output control circuit adapted to provide a control signal that controls the output of said TAP output multiplexer;
• an internal scan observe register coupled to said TAP output control circuit, said internal scan observe register adapted to provide internal scan test directions to said output control circuit when said TAP controller internal scan test system is operating in internal scan test mode;
• a TAP state machine coupled to said internal scan observe register, said TAP state machine adapted to control the state of said test access port (TAP) controller system;
• a bypass register coupled to said TAP state machine, said bypass register adapted to provide a bypass path between a test data in port and a test data out port;
• an IDcode register coupled to said TAP state machine, said IDcode register adapted to store information associated with identifying an integrated circuit;
• an instruction holding register coupled to said TAP state machine, said instruction holding register adapted to store an instruction;
• and
• an instruction shift register coupled to said TAP state machine, said instruction shift register adapted to shift said instruction.

A test access port (TAP) controlled internal scan test intermediate debugging system comprising:

• an intermediate TAP controller internal scan test system adapted to transmit an indicated intermediate scan test chain signal off of an integrated circuit as a test data out signal, said intermediate TAP controller internal scan test system includes an internal scan observe register, said internal scan observe register controls the selection of an intermediate internal scan test input signal;
• a plurality of design circuit blocks coupled to said intermediate TAP controller internal scan test system, said plurality of design circuit blocks adapted to perform designated functions during normal operation mode and include scan test elements adapted to shift in scan test vectors, capture resulting scan test information and shift out the scan test results during scan test operations;
• a scan test chain primary input pin coupled to one of said plurality of design circuit blocks, said scan test chain primary input pin adapted to provide a communication port for scan test input information;
• and
• a scan test chain final output pin coupled to one of said plurality of design circuit blocks, said scan test chain final output pin adapted to provide a communication port for scan test output information.

A TAP controlled internal scan test intermediate debugging method comprising the steps of:

• receiving an intermediate scan test chain signal by a TAP controller from a scan test chain;
• selecting said intermediate scan test chain signal for transmission off of an integrated circuit in accordance with instructions from a scan observe register;
• and
• transmitting said intermediate scan test chain signal off of an integrated circuit through a TAP controlled test data out (TDO) port.