Statistical counters in high speed network integrated circuits

A method, comprising:

• incrementing only one N-bit register in a first counter group in a clock cycle in response to a first input received, the first input being one of a first set of inputs designated to be received by the first counter group;
• incrementing a first adder in response to incrementing the only one N-bit register in the first counter group;
• incrementing only one N-bit register in a second counter group in the clock cycle in response to a second input received, the second input being one of a second set of inputs designated to be received by the second counter group, the second input being different from the first input;
• and
• incrementing a second adder in response to incrementing the only one N-bit register in the second counter group.

An article of manufacture, comprising a machine-accessible medium including data that, when accessed by a machine, cause the machine to perform the operations comprising:

• incrementing only one N-bit register in a first counter group in a clock cycle in response to a first input received, the first input being one of a first set of inputs designated to be received by the first counter group;
• incrementing a first adder in response to incrementing the only one N-bit register in the first counter group;
• incrementing only one N-bit register in a second counter group in the clock cycle in response to a second input received, the second input being one of a second set of inputs designated to be received by the second counter group, the second input being different from the first input;
• and
• incrementing a second adder in response to incrementing the only one N-bit register in the second counter group.