Soft error detection in high speed microprocessors
AssigneeInternational Business Machines Corporation
InventorsPaul J. Jordan, Peter J. Klim
Life of this patent
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Abstract
Aspects for soft error detection for a superscalar microprocessor are described. The aspects include a first pipeline, the first pipeline including a first arithmetic logic unit, ALU, comparator and a first general purpose register, GPR, for storing first data, and a second pipeline, the second pipeline including a second GPR and a second ALU comparator, the second GPR for storing second data, the second data being a copy of the first data. A detection system utilizes one of the first and second ALU comparators to perform a comparison of the second data with the first data during an idle state of the first and second pipelines.
Claims20
A soft error detection system for a superscalar microprocessor comprising:
- a first pipeline, the first pipeline including a first arithmetic logic unit, ALU, comparator and a first general purpose register, GPR, for storing first data;
- a second pipeline, the second pipeline including a second GPR and a second ALU comparator, the second GPR for storing second data, the second data being a copy of the first data;
- and
- a detection system utilizing one of the first and second ALU comparators to perform a comparison of the second data with the first data during an idle state of the first and second pipelines.
A method for detecting soft errors in superscalar microprocessors, the method comprising:
- utilizing duplicated register files to store data in first and second pipelines of a processor;
- and
- comparing data from a same entry in the duplicated register files with an arithmetic logic unit of one of the first and second pipelines to detect a soft error in the duplicated register files.
A method for soft error detection in a high frequency superscalar microprocessor, the method comprising:
- determining an idle state condition in first and second fixed point unit pipelines;
- reading data from a first general purpose register of the first fixed point unit pipeline;
- and
- comparing the read data with corresponding duplicate data in a second general purpose register of the second fixed point unit pipeline with an arithmetic logic unit of the second fixed point unit pipeline.
Dependencies are inferred from the claim text.