Systems and methods for use in reduced instruction set computer processors for retrying execution of instructions resulting in errors

A system for use in a RISC data processing system for retrying the execution of an instruction having an instruction fetch address if an error is detected in the execution of the instruction, wherein said data processing system comprises a pipeline with multiple stages, and said system comprising:

• a program counter for sequentially providing an instruction fetch address of each of a plurality of instructions to be fetched;
• a pipeline history cache that stores said instruction fetch address of each instruction;
• an execution unit for executing or at least partially executing each instruction to thereby generate a result for the respective instruction;
• a comparator, responsive to said execution unit, that validates the result of each instruction prior to a state change for the respective instruction and prior to said execution unit executing or at least partially executing each subsequent instruction;
• and
• error recovery logic, responsive to said comparator, that triggers said program counter to obtain said instruction fetch address of an instruction stored in said pipeline history cache if an error is detected by said comparator following the execution of the respective instruction, such that the respective instruction can again be fetched and such that said execution unit will re-execute or at least partially re-execute the respective instruction.