Processor with redundant logic

A data processing system including processing means connected to a system memory, wherein the processing means comprises:

• a central processor on a die;
• a memory interface on the die connected to the central processor and connectable to a system memory;
• a pipelined memory access bus connected to the memory interface and including a plurality of stages;
• a set of attached processors on the die wherein each of the set of attached processors is connected to a corresponding stage of the memory access bus and capable of directly accessing the system memory, wherein each of the attached processors is initially enabled to perform memory transfers and further wherein each of the attached processors is capable of being programmably disabled;
• and
• a redundant processor on the die connected to the memory access bus, wherein the redundant processor is functionally equivalent to at least one of the attached processors and wherein the redundant processor is initially disabled from performing memory transfers and wherein the redundant processor is capable of being programmably enabled when of the attached processors is disabled such that the enabled redundant processor replaces the disabled attached processor.

A single chip data processing system comprising:

• a central processor on a die connectable to a system memory via a memory interface;
• a set of functionally equivalent vector processors on the die each connected to the memory interface via a memory access bus to provide vector processing functionality to the general purpose processor, wherein each of the vector processors is associated with a corresponding processor ID and further wherein each of the vector processors is configured to be programmably disabled from the memory access bus upon determining that the vector processor is faulty;
• and
• a redundant processor on the die and connectable to the memory interface via the memory access bus, wherein the redundant vector processor is functionally equivalent to each of the set of vector processors and further wherein the redundant processor includes a programmable processor ID suitable for storing the processor ID of the faulty vector processor
• the memory access bus comprises a pipelined bus including a set of stages defined by a corresponding set of latches and further wherein each of the vector processors is attached to a unique stage of the pipelined bus.