Raid memory

A method of controlling a memory system comprising a plurality of memory cartridges and, a plurality of memory controllers, wherein each memory controller is coupled to a respective one of the plurality of memory cartridges, wherein each of the memory cartriges contains X4 memory chips, the method comprising the acts of:

• (a) during a memory transaction, correcting single bit errors in each of the plurality of memory cartridges using error correction code;
• and
• (b) during the memory transaction, correcting a multi-bit error in one of the plurality of memory cartridges using an exclusive or engine.

A method of controlling a memory system comprising a plurality of memory cartridges and a plurality of memory controllers, wherein each memory controller is coupled to a respective one of the plurality of memory cartridges, wherein each of the memory cartridges contains X8 memory chips, the method comprising the acts of:

• (a) during a memory transaction, detecting an error in one of the plurality of memory cartridges using error correction code;
• and
• (b) during the memory transaction, correcting the error in one of the plurality of memory cartridges using an exclusive OR engine.

A device for controlling a memory system comprising a plurality of memory cartridges and, a plurality of memory controllers, wherein each memory controller is coupled to a respective one of the plurality of memory cartridges, wherein each of the memory cartridges contains X4 memory chips, the device comprising:

• means for correcting single bit errors in each of the plurality of memory cartridges during a memory transaction;
• and
• means for correcting a multi-bit error in one of the plurality of memory cartridges during a memory transaction.

A device for controlling a memory system comprising a plurality of memory cartridges and, a plurality of memory controllers, wherein each memory controller is coupled to a respective one of the plurality of memory cartridges, wherein each of the memory cartridges contains X8 memory chips, the device comprising:

• means for detecting an error in one of the plurality of memory cartridges during a memory transaction;
• and
• means for correcting the error in one of the plurality of memory cartridges during the memory transaction.

A computer system comprising:

• a host/data controller;
• and
• a memory system coupled to the host/data controller, the memory system comprising a plurality of removable memory cartridges, each of the plurality of removable memory cartridges adapted to contain at least one semiconductor memory device and a respective memory controller, wherein the host/data controller transitions the memory system from a redundant mode of operation to a non-redundant mode of operation to facilitate removal of one of the plurality of removable memory cartridges while the computer system is operating.