Apparatus and method for a low power, multi-level GTL I/O buffer with fast restoration of static bias

An apparatus, comprising:

• a buffer having
• a dynamic bias circuit to clamp a voltage level at an I/O buffer pad to a termination voltage level Vtt, selected according to a mode signal, in response to a rising signal transition, by pulling down a pbias node voltage from a static voltage level to a dynamic voltage level, such that the voltage level at the buffer pad is prevented from overshooting the Vtt voltage level;
• a static bias circuit to maintain the pbias node voltage at the static voltage level;
• and
• a dynamic resistance unit to generate a dynamic resistance to reduce an RC time constant required to pull up the pbias node voltage from the dynamic voltage level to the static voltage level once the rising signal transition is complete to reduce power consumption required to clamp the voltage level at the buffer pad to the Vtt voltage level.

A system comprising:

• a front side bus coupling a processor to chipset via a chipset front side bus;
• a plurality of front side bus buffers including:
• a dynamic bias circuit to clamp a voltage level at a buffer pad to a termination voltage level Vtt, selected according to a mode signal, in response to a rising signal transition, by pulling down a pbias node voltage from a static voltage level to a dynamic voltage level, such that the voltage level at the buffer pad is prevented from overshooting the Vtt voltage level;
• a static bias circuit to maintain the pbias node voltage at the static voltage level;
• and
• a dynamic resistance unit to generate a dynamic resistance to reduce an RC time constant required to pull up the pbias node voltage from the dynamic voltage level to the static voltage level once the rising signal transition is complete to reduce power consumption required to clamp the voltage level at the buffer pad to the Vtt voltage level.

A dual mode GTL interface signaling buffer comprising:

• a dynamic bias circuit to clamp a voltage level at an I/O buffer pad to a termination voltage level Vtt, in response to a rising signal transition, by pulling down a pbias node voltage from a static voltage level to a dynamic voltage level, such that the voltage level at the buffer pad is prevented from overshooting the Vtt voltage level;
• a static bias circuit to maintain the pbias node voltage at the static voltage level;
• and a dynamic resistance unit to generate a dynamic resistance to reduce an RC time constant required to pull up the pbias node voltage from the dynamic voltage level to the static voltage level once the rising signal transition is complete to reduce power consumption required to clamp the voltage level at the buffer pad to the Vtt voltage level;
• and
• a mode selection unit to receive a mode signal indicating a selected static voltage level of the pbias node, and to supply the selected static voltage level to the pbias node.