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US 6,785,793 B2Granted
Method and apparatus for memory access scheduling to reduce memory access latency
AssigneeIntel Corporation
InventorsNagi Aboulenein, Randy B. Osborne, Ram Huggahalli, Vamsee K. Madavarapu, Ken M. Crocker
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Abstract
A device is presented including a memory controller. The memory controller is connected to a read request queue. A command queue is coupled to the memory controller. A memory page table is connected to the memory controller. The memory page table has many page table entries. A memory page history table is connected to the memory controller. The memory history table has many page history table entries. A pre-calculated lookup table is connected to the memory controller. The memory controller includes a memory scheduling process to reduce memory access latency.
Claims56
An apparatus comprising:
- a memory controller having scheduling means for reducing memory access latency and enhancing bandwidth;
- a read request queue coupled to the memory controller;
- a command queue coupled to the memory controller;
- and a memory page table coupled to the memory controller, the page table having a plurality of page table entries, the plurality of page table entries having a structure to store a memory page number, a memory page validity status, a memory page closed status, and an index to point to a slot in a shift register in the command queue.
1 more element
An apparatus comprising:
- a memory controller;
- a read request queue coupled to the memory controller;
- a command queue coupled to the memory controller;
- a memory page table coupled to the memory controller, the memory page table having a plurality of page table entries;
- a memory page history table coupled to the memory controller, the memory history table having a plurality of page history table entries, the plurality of page table entries having a structure to store a memory page number, a memory page validity status, a memory page closed status, and an index to point to a slot in a shift register in the command queue;
- and
- a pre-calculated lookup table coupled to the memory controller;
- wherein the memory controller including a memory scheduling process to reduce memory access latency.
5 more elements
A system comprising:
- a processor;
- a memory controller coupled to the processor;
- a bus coupled to the memory controller;
- a memory coupled to the bus and the memory controller;
- scheduling means for reducing memory access latency;
- a read request queue coupled to the memory controller;
- a command queue coupled to the memory controller;
- and
- a memory page table coupled to the memory controller, the page table having a plurality of page table entries, the plurality of page table entries having a structure to store a memory page number, a memory page validity status, a memory page closed status, and an index to point to a slot in a shift register in the command queue.
6 more elements
A system comprising:
- a processor;
- a memory controller coupled to the processor;
- a bus coupled to the memory controller;
- a memory coupled to the bus and the memory controller;
- a read request queue coupled to the memory controller;
- a command queue coupled to the memory controller;
- a memory page table coupled to the memory controller, the page table having a plurality of page table entries;
- a memory page history table coupled to the memory controller, the memory history table having a plurality of page history table entries, the plurality of page table entries having a structure to store a memory page number, a validity status, a memory page closed status, and an index to point to a slot in a shift register in the command queue;
- and
- a pre-calculated lookup table coupled to the memory controller, wherein the memory controller including a memory scheduling process to reduce memory access latency.
7 more elements
A method comprising:
- determining one of scheduling automatic precharge of at least one memory page and preventing scheduling automatic precharge of at least one memory page;
- predicting when to keep at least one memory page open for access by a memory controller;
- scheduling insertion for each of a plurality of memory commands independently into a memory command stream while relaxing a plurality of memory command timing constraints;
- performing initiation of opportunistic memory write-command flush sequences;
- and
- processing out-of-order page-oriented memory read requests.
3 more elements
An apparatus comprising a machine-readable medium containing instructions which, when executed by a machine, cause the machine to perform operations comprising:
- determining one of scheduling automatic precharge of at least one memory page and preventing scheduling automatic precharge of at least one memory page;
- predicting when to keep at least one memory page open for access by a memory controller;
- scheduling insertion for each of a plurality of memory commands independently into a memory command stream while relaxing a plurality of memory command timing constraints;
- performing initiation of opportunistic memory write-command flush sequences;
- and
- processing out-of-order page-oriented memory read requests.
3 more elements
An apparatus comprising:
- a memory controller having scheduling means for reducing memory access latency and enhancing bandwidth,
- a read request queue coupled to the memory controller;
- a command queue coupled to the memory controller;
- and a memory page table coupled to the memory controller, the page table having a plurality of page table entries,
- a memory page history table coupled to the memory controller, the memory history table having a plurality of page history table entries, the plurality of page history table entries having a structure to store a memory page number, an in-use status, a first number of conflict-free accesses, a second number of conflict-free accesses, and a coverage.
2 more elements
An apparatus comprising:
- a memory controller having scheduling means for reducing memory access latency and enhancing bandwidth, wherein the scheduling means for reducing memory latency comprises an opportunistic write-flushing policy, the opportunistic write-flushing policy having opportunistic initiation of write-flush sequences, preemption of write-flush sequences upon receipt of new read requests, write block-out periods, and non-first-in-first-out (FIFO) write selection.
An apparatus comprising:
- a memory controller;
- a read request queue coupled to the memory controller;
- a command queue coupled to the memory controller;
- a memory page table coupled to the memory controller, the memory page table having a plurality of page table entries, the plurality of page history table entries having a structure to store a memory page number, an in-use status, a first number of conflict-free accesses, a second number of conflict-free accesses, and a coverage;
- a memory page history table coupled to the memory controller, the memory history table having a plurality of page history table entries;
- and
- a pre-calculated lookup table coupled to the memory controller;
- wherein the memory controller including a memory scheduling process to reduce memory access latency.
5 more elements
Dependencies are inferred from the claim text.