Techniques for increasing bandwidth in port-per-module memory systems having mismatched memory modules

A method for accessing a single port memory core of a memory component on a memory module, the memory component having first and second sets of interface connections for providing access to the single port memory core, the method comprising the steps of:

• receiving at least one memory access control signal at the memory module;
• and
• decoding the at least one memory access control signal so as to select between a first mode wherein a first portion of the single port memory core is accessible through the first set of interface connections and a second portion of the single port memory core is accessible through the second set of interface connections, and a second mode wherein both the first portion and the second portion of the single port memory core are accessible through the first set of interface connections.

A memory module for storing data thereon, the memory module comprising:

• at least one single port memory component for providing a first group of memory storage locations and a second group of memory storage locations;
• and
• memory access circuitry for selecting between a first mode wherein the first group of memory storage locations is accessible through a first set of memory module interface connections and the second group of memory storage locations is accessible through a second set of memory module interface connections, and a second mode wherein both the first group and the second group of memory storage locations are accessible through the first set of memory module interface connections.

A method for accessing memory storage locations of at least one single port memory component on a memory module, the method comprising the steps of:

• receiving at least one memory access control signal;
• and
• decoding the at least one memory access control signal so as to select between a first mode wherein the first group of memory storage locations is accessible through a first set of memory module interface connections and the second group of memory storage locations is accessible through a second set of memory module interface connections, and a second mode wherein both the first group and the second group of memory storage locations are accessible through the first set of memory module interface connections.

A method for accessing a single port memory core of a memory component on a memory module, the memory component having first and second sets of memory component interface connections for providing access to the single port memory core, the memory module having first and second sets of memory module interface connections for providing access to the first and second sets of memory component interface connections, respectively, the method comprising the steps of:

• receiving at least one memory access control signal;
• and
• decoding the at least one memory access control signal so as to select between a first mode wherein a first portion of the single port memory core is accessible through the first set of memory component interface connections and a second portion of the single port memory core is accessible through the second set of memory component interface connections, and a second mode wherein both the first portion and the second portion of the single port memory core are accessible through the first set of memory component interface connections.

A memory module for storing data thereon, the memory module comprising:

• a memory component having a first set of interface connections for providing access to a single memory core of the memory component and a second set of interface connections for providing access to the single memory core of the memory component;
• memory access circuitry for selecting between a first mode wherein a first portion of the single memory core is accessible through the first set of interface connections and a second portion of the single memory core is accessible through the second set of interface connections, and a second mode wherein both the first portion and the second portion of the single memory core are accessible through the first set of interface connections.

A method for accessing a single memory core of a memory component on a memory module, the memory component having first and second sets of interface connections for providing access to the single memory core, the method comprising the steps of:

• receiving at least one memory access control signal;
• and
• decoding the at least one memory access control signal so as to select between a first mode wherein a first portion of the single memory core is accessible through the first set of interface connections and a second portion of the single memory core is accessible through the second set of interface connections, and a second mode wherein both the first portion and the second portion of the single memory core are accessible through the first set of interface connections.

A method for accessing a single memory core of a memory component on a memory module, the memory component having first and second sets of memory component interface connections for providing access to the single memory core, the memory module having first and second sets of memory module interface connections for providing access to the first and second sets of memory component interface connections, respectively, the method comprising the steps of:

• receiving at least one memory access control signal;
• and
• decoding the at least one memory access control signal so as to select between a first mode wherein a first portion of the single memory core is accessible through the first set of memory component interface connections and a second portion of the single memory core is accessible through the second set of memory component interface connections, and a second mode wherein both the first portion and the second portion of the single memory core are accessible through the first set of memory component interface connections.