Read/write alignment scheme for port reduction of multi-port SRAM cells
AssigneeInternational Business Machines Corporation
InventorsJens Leenstra, Juergen Pille, Rolf Sautter, Dieter Wendel
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AssigneeInternational Business Machines Corporation
InventorsJens Leenstra, Juergen Pille, Rolf Sautter, Dieter Wendel
Estimating the term…
A considerable amount of area can be saved according to the present invention by reducing the number of input ports and the number of output ports to the number n of concurrently intended array accesses. This remarkable reduction of ports and thus an extraordinary associated area saving can be achieved when some knowledge about array utilization is exploited: The array accesses are to be performed with concurrent accesses from at most k particular groups. A group is defined by a plurality of array accesses which have at most one access to the same port at a time. Then, for reading the read results are aligned according to a simple re-wiring scheme to the respective read requesters, whereas for writing the accesses are aligned prior to the array access according to the same or a similar scheme.
A method for efficiently accessing multi-port cell array circuitry, each cell of said array being usable by an at least n-times multiple concurrent access, the method comprising:
A hardware circuit comprising a multi-port array storage device usable by a n1-times concurrent write access, and a n2-times concurrent read access, said storage device being characterized by comprising:
A computer system having a microprocessor device, said microprocessor device having one or more subunits, at least one subunit of said one or more subunits having one or more hardware circuits, at least one hardware circuit of said one or more hardware circuits comprising a multi-port array storage device usable by a n1-times concurrent write access, and a n2-times concurrent read access, said storage device comprising:
Dependencies are inferred from the claim text.