Distributed processor memory module and method

A memory module for use in a computer system, the memory module comprising:

• a substrate adapted for coupling to the computer system through a computer system data bus and a computer system address bus, the system data bus having a first data width;
• a program memory coupled to the computer system data bus and the computer system address bus, the program memory being structured to store instructions on the data bus responsive to a first set of addresses on the computer system address bus;
• a system memory mounted on the substrate and coupled to the computer system data buts and the computer system address bus, the system memory being structured to transfer data to and from the computer system data bus responsive to a second set of addresses on the computer system address bus, at least some of the addresses in the second set being different from the addresses in the first set;
• a program memory controller coupled to the program memory to transfer instructions from the program memory;
• and
• a plurality of processors coupled to the system memory through a processor/system memory data bus having a second data width grater than the first data width and further coupled to the program memory controller to have access through the program memory controller to instructions stored in the program memory, each processor being structured to execute instructions from the program memory and, when executing the instructions, access the system memory through the processor/system memory data bus.

A computer system, comprising:

• a central processing unit;
• a display system;
• a peripheral bus;
• at least one mass storage device coupled to the peripheral bus;
• at least one user interface device coupled to the peripheral bus;
• a bus bridge coupled to the central processing unit and the peripheral bus, the bus bridge being structured to allow communication between the central processing unit and the at least one mass storage device, the at least one use interface device and the display system;
• and
• a memory module coupled to the central processing unit, the memory module comprising:
• a memory interface adapted to interface with the central processing unit through the bus bridge and having a data bus having a first data width, the memory interface coupling data to and from the bus bridge and coupling addresses from the bus bridge;
• a program memory coupled to the memory interface, the program memory being structured to store data representative of instructions responsive to a first set of addresses from the bus bridge;
• a program memory controller coupled to the program memory and structured to transfer instructions from the program memory;
• and
• a plurality of memory/processing units, each of which includes a processor coupled to a system memory through a memory/processing data bus having a second data width greater than the first data width, the processor being coupled to the program memory controller to have access through the program memory controller to instructions stored in the program memory and being further coupled to the system memory to allow the processor to access the system memory, the system memory further being coupled to transfer data to and from the bus bridge and being coupled to receive addresses from the bus bridge, the system memory being accessed through the bus bridge responsive to a second set of addresses from the bus bridge, at least some of the addresses in the second set being different from the addresses in the first set.

A method of improving the capabilities of a computer system having a circuit board containing at least one memory module removably mounted on the circuit board, the memory module communicating with the circuit board through a data bus having a first data width and an address bus, the method comprising:

• removing the at least one removable memory module from the circuit board;
• installing a replacement memory module on the circuit board, the replacement memory module including a program memory, a program memory controller coupled to the program memory, and a plurality of memory/processing units, each of which includes a processor coupled to a system memory through a memory/processing data bus having a second data width greater than the first data width, the processor being coupled to the program memory controller to have access through the program memory controller to instructions stored in the program memory and being further coupled to the system memory to allow the processor to access the system memory via the memory/processing data bus, the system memory further being coupled to transfer data to and from the data bus of the circuit board and being coupled to receive addresses from the address bus of the circuit board;
• storing a processing algorithm in the computer system;
• transferring instructions corresponding to the processing algorithm to the program memory by addressing the programming memory using the first set of addresses;
• transferring under the control of the program memory controller the instructions stored in the program memory to the processor for execution of the processing algorithm;
• and
• accessing the system memory through the circuit board responsive to a second set of addresses from the address bus of the circuit board, at least some of the addresses in the second set being different from the addresses in the first set.

A method of accessing and processing data in a system memory of a computer system, the system memory being mounted on a memory module that is coupled to the computer system through a data bus having a first data width and an address bus, the method comprising:

• mounting a program memory on the memory module;
• mounting a program memory controller coupled to the program memory on the memory module;
• mounting a plurality of processors on the memory module and coupling each processor to the system memory through a processor/system memory data bus having a second data width greater than the first data width and further coupling the processors to the program memory controller;
• transferring instructions from the data bus to the program memory responsive to a first set of addresses on the address bus;
• providing access to the instructions stored in the program memory through the program memory controller;
• allowing the processor to execute the stored instructions;
• and
• transferring data between the data bus and the system memory responsive to a second set of addresses on the address bus, at least some of the addresses in the second set being different from the addresses in the first set.