Use of a cache coherency mechanism as a doorbell indicator for input/output hardware queues
AssigneeUnisys Corporation
InventorRobert M. Malek
Life of this patent
Estimating the term…
Abstract
A method of and apparatus for improving the scheduling efficiency of a data processing system using the facilities which maintain coherency of the system's level cache memories. These efficiencies result from monitoring the cache memory lines which indicate invalidation of a cache memory entry because of a storage operation within backing memory. This invalidity signal is utilized to generate a doorbell type interface indication of a new application entry within the work queue.
Claims25
In a data processing system with a main system memory and having a work queue located within said main system memory having a cache memory and having a cache memory coherency facility with a cache line which indicates a store operation to a memory location associated with said cache memory, the improvement comprising:
- a. a scheduling facility responsively coupled to said cache line which informs said data processing system of an entry into said work queue in response to said cache line indicating a store operation to said memory location.
A data processing system comprising:
- a. A main system memory containing a work queue;
- b. A cache memory;
- c. A cache memory line responsively coupled to said cache memory which indicates a store operation at a location associated with said cache memory;
- and
- c. A scheduler responsively coupled to said work queue and said cache memory line which signals an entry into said work queue in response to said cache memory line indicating a store operation at said location.
A method of scheduling with a data processing system having a cache memory coherency facility comprising:
- a. monitoring said cache memory coherency facility for storage of data into a work queue;
- and
- b. generating a doorbell type interface indication of a new entry in said work queue in response to said monitoring step.
A method of scheduling with a data processing system having a cache memory coherency facility comprising:
- a. monitoring said cache memory coherency facility for storage of data into a work queue;
- b. generating a doorbell type interface indication of a new entry in said work queue in response to said monitoring step;
- c. wherein said cache memory coherency facility further comprises Modified/Exclusive/Shared/Invalid protocol;
- d. wherein said generating step provides said doorbell type interface indication to a Host Channel Adaptor (HCA);
- e. wherein said Host Channel Adaptor further comprises an Infiniband Host Channel Adaptor;
- and
- f. wherein said generating step further comprises providing an offset pointer.
A data processing apparatus comprising:
- a. queuing means for queuing application service requests;
- b. storing means for storing cache memory data;
- c. indicating means responsively coupled to said storing means for indicating a store operation at a location associated with said storing means;
- and
- d. signaling means responsively coupled to said queuing means and said indicating means for signaling an entry into said queuing means in response to said indicating means indicating a store operation at said location.
An apparatus for managing data storage and transfers within a system having cached memory comprising:
- a. a main system memory;
- b. a work queue located within said main system memory;
- c. a cache memory;
- d. a cache memory line responsively coupled to said cache memory which indicates a store operation at a location associated with said cache memory;
- e. a scheduler responsively coupled to said work queue and said cache memory line which signals an entry into said work queue in response to said cache memory line indicating a store operation at said location;
- and
- f. an offset pointer generated by said scheduler which indicates location of said entry.
Dependencies are inferred from the claim text.