High performance symmetric multiprocessing systems via super-coherent data mechanisms

A multiprocessor data processing system comprising:

• a plurality of processing units including a first processing unit;
• a memory hierarchy including a plurality of caches, wherein each cache is affiliated with one of said plurality of processing units;
• coupling means for interconnecting said plurality of processing units;
• processing logic, responsive to a receipt of a first system bus response to a coherency operation, for executing operations on a processing unit of said multiprocessor data processing system utilizing super-coherent data, wherein said super-coherent data is data that is present in a first cache associated with said first processting unit while a second processing unit is actively modifying the data at a second cache;
• and
• means for enabling coherent operations with other processing units responsive to an occurence of a pre-determined condition.

A method for improving coherency operations within a multiprocessor data processing system comprising:

• setting a cache line of a first processor to a first coherency state that indicates that modification of data within a shared cache line of a second cache of a second processor has been snooped on a system bus of said data processing system;
• issuing a request for said cache line as a Z1 read on a system bus, responsive to said cache line being in said first coherency state;
• responsive to a receipt of a response indicating that said second processor is currently modifying said cache line within said second cache and that said first processor should utilize data currently available within said cache line, changing said first coherency state to a second coherency state, wherein said second coherency state indicates to said first processor that a first processor's request for said cache line should utilize the data currently within the first processor's cache and that the request is not to be sent to said system bus;
• and
• responding to said request with data of said cache line when said cache line indicates said second coherency state.

A multiprocessor data processing system comprising:

• a plurality of processors each having a cache that supports coherency operations;
• a system bus interconnecting said plurality of cache lines;
• and
• operational logic that provides:
• means for setting a cache line oh first processor to a first coherency state that indicates that modification of data within a shared cache line of a second cache of a second processor has been snooped on a system bus of said data processing system;
• means for issuing a request for said cache line as a Z1 read on a system bus, responsive to said cache line being in said first coherency state;
• means responsive to receipt of a response indicating that said second processor is currently modifying said cache line within said second cache and that said first processor should utilize data currently available within said cache line, for changing said first coherency state to a second coherency state, wherein said second coherency state indicates to said first processor that a first processor's request for said cache line should utilize the data currently within the first proccssor' cache and that Like request is not to be sent to said system bus;
• and
• means for responding to said request with data of said cache line when said cache line indicates said second coherency state.