US 6,785,770 B2 · Data processing apparatus with a cache memory and method of using such an apparatus

Abstract

A data processing apparatus has a main memory that contains memory locations with mutually different access latencies. Information from the main memory is cached in a cache memory. When cache replacement is needed selection of a cache replacement location depends on differences in the access latencies of the main memory locations for which replaceable cache locations are in use. When an access latency of a main memory location cached in the replaceable cache memory location is relatively smaller than an access latency of other main memory locations cached in other replaceable cache memory locations, the cached data for that main memory location is replaced by preference over data for the other main memory locations, because of its smaller latency.

Claims11

Dependent claims

A method of managing a cache memory in a processor that has a main memory that contains memory locations with a plurality of access latencies, the method comprising the steps of:

selecting of a cache replacement location in dependence on differences in respective access latencies of the main memory locations for which replaceable cache locations are in use;
using an address tag of data stored in the cache memory to determine the respective access latency of a respective main memory location;
and
placing a preference to replacement of a replaceable cache memory location according to whether the respective access latency of the respective main memory location cached in the replaceable cache memory location is smaller than another access latency of another main memory locations, cached in another replaceable cache memory location.

1 more element

A data processing apparatus, comprising:

a processor;
a main memory having an address space which addresses locations having at least two access latencies;
a cache memory between the main memory and the processor;
and
a cache management unit arranged to select a cache replacement location from replaceable cache memory locations in the cache memory, wherein the cache management unit selects the cache replacement location dependent on the relative access latencies of the main memory locations cached in the cache locations, the relative access latencies being determined from an address tag of data stored in the cache locations, a preference being given being given to replacement of a replaceable cache memory location according to whether an access latency of a main memory location cached in the replaceable cache memory location is relatively smaller than an access latency of other main memory locations, cached in other replaceable cache memory locations.

2 more elements

Dependencies are inferred from the claim text.

Data processing apparatus with a cache memory and method of using such an apparatus

Life of this patent

Data processing apparatus with a cache memory and method of using such an apparatus

Life of this patent

Abstract

Claims11