Method and apparatus for servicing massive interrupts in random access memory (RAM)

An apparatus for servicing massive interrupts in random access memory (RAM), comprising:

• means for receiving a massive interrupt signal;
• means for reading at least one unit interrupt register in a first RAM area in response to the massive interrupt signal, wherein a set unit interrupt bit corresponds to an address in a second RAM area;
• means for reading at least one interrupt status register at the corresponding address in the second RAM area in response to the set unit interrupt bit, wherein a set interrupt status bit corresponds to an address in a third RAM area;
• means for reading at least one interrupt cause bit at the corresponding address in the third RAM area in response to the set interrupt status bit, wherein detailed information is obtained about an interrupt;
• and
• means for servicing the interrupt in response to the detailed information.

A computer readable medium containing executable instructions which, when executed in a processing system, cause the processing system to service massive interrupts in random access memory (RAM) by:

• receiving a massive interrupt signal;
• reading at least one unit interrupt register in a first RAM area in response to the massive interrupt signal, wherein a set unit interrupt bit corresponds to an address in a second RAM area;
• reading at least one interrupt status register at the corresponding address in the second RAM area in response to the set unit interrupt bit, wherein a set interrupt status bit corresponds to an address in a third RAM area;
• reading at least one interrupt cause bit at the corresponding address in the third RAM area in response to the set interrupt status bit, wherein detailed information is obtained about an interrupt;
• servicing the interrupt in response to the detailed information.

An electromagnetic medium containing executable instructions which, when executed in a processing system, cause the processing system to service massive interrupts in random access memory (RAM) by:

• receiving a massive interrupt signal;
• reading at least one unit interrupt register in a first RAM area in response to the massive interrupt signal, wherein a set unit interrupt bit corresponds to an address in a second RAM area;
• reading at least one interrupt status register at the corresponding address in the second RAM area in response to the set unit interrupt bit, wherein a set interrupt status bit corresponds to an address in a third RAM area;
• reading at least one interrupt cause bit at the corresponding address in the third RAM area in response to the set interrupt status bit, wherein detailed information is obtained about an interrupt;
• servicing the interrupt in response to the detailed information.