Status register to improve initialization of a synchronous memory
AssigneeMicron Technology, Inc.
InventorFrankie F. Roohparvar
Life of this patent
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Abstract
A synchronous flash memory includes an array of non-volatile memory cells. The memory device has a package configuration that is compatible with an SDRAM. The memory device in one embodiment can comprise control circuitry to perform an initialization operation on the synchronous memory, and a status register having at least one data bit that can be programmed to indicate if the initialization is being performed. A method of operating a memory system includes initiating an initialization operation on a memory device, and monitoring a memory status register to determine when the initialization operation is completed.
Claims14
A synchronous memory comprising:
- control circuitry to perform an initialization operation on the synchronous memory;
- a status register having at least one data bit that is in a first state during initialization and an inverse state after initialization has been completed;
- non-volatile elements to store data;
- and
- volatile registers coupled to receive the data from the non-volatile elements during the initialization operation.
A synchronous memory comprising:
- control circuitry to perform an initialization operation on the synchronous memory;
- a status register having at least one data bit that is in a first state during initialization and an inverse state after initialization has been completed;
- a data output connection, wherein the at least one data bit of the status register is provided on the data output connection in response to an externally provided command;
- non-volatile elements to store data;
- and
- volatile registers coupled to receive the data from the non-volatile elements during the initialization operation.
A memory system comprising:
- a memory controller;
- and
- a synchronous memory coupled to the memory controller and comprising,
- control circuitry to perform an initialization operation on the synchronous memory;
- a status register having at least one data bit that is in a first state during initialization and an inverse state after initialization has been completed;
- a data output connection coupled to the memory controller, wherein the at least one data bit of the status register is provided on the data output connection in response to a command provided by the memory controller;
- non-volatile elements to store data;
- and
- volatile registers coupled to receive the data from the non-volatile elements during the initialization operation.
A synchronous memory comprising:
- control circuitry to perform an initialization operation on the synchronous memory;
- a status register having at least one data bit that indicates when an initialization operation has been completed;
- non-volatile elements to store data;
- and
- volatile registers coupled to receive the data from the non-volatile elements during the initialization operation.
Dependencies are inferred from the claim text.