System and method for machine specific register addressing in a split transactional unidirectional bus architecture

An integrated circuit comprising:

• a plurality of bus devices capable of transferring data with one another;
• and
• a bus interface unit for transferring machine specific register (MSR) requests between said plurality of bus devices, said bus interface unit comprising:
• a plurality of input ports capable of receiving incoming MSR requests from said plurality of bus devices;
• a plurality of output ports capable of transmitting data to said plurality of bus devices;
• and
• a controller capable of reading N routing bits associated with a first received MSR request and comparing a first identification (ID) value in a predetermined M-bit field in said N routing bits to a first designated value, wherein said controller, in response to a determination that said first ID value does not equal said first designated value:
• 1) realigns said N routing bits such that remaining ones of the N-M bits outside said predetermined M-bit field are moved into said predetermined M-bit field and 2) transmits said realigned N routing bits via a first one of said plurality of output ports identified by said first ID value.

For use in a bus interface unit having a plurality of input ports and a plurality of output ports coupled to a plurality of bus devices, a method of transferring machine specific register (MSR) requests between said plurality of bus devices, the method comprising the steps of:

• receiving incoming MSR requests from the plurality of bus devices
• reading N routing bits associated with a first received MSR request;
• comparing a first identification (ID) value in a predetermined M-bit field in the N routing bits to a first designated value;
• and
• in response to a determination that the first ID value does not equal the first designated value:
• 1) realigning the N routing bits such that remaining ones of the N-M bits outside the predetermined M-bit field are moved into the predetermined M-bit field and 2) transmitting the realigned N routing bits via a first one of the plurality of output ports identified by the first ID value.