Simultaneous dual rail static carry-save-adder circuit using silicon on insulator technology

A data processing system, comprising:

• a memory;
• a central processing unit;
• at least one execution unit included within said central processing unit for performing arithmetic and logical operations;
• an arithmetic circuit within said at least one execution unit which performs arithmetic operations on data stored in said memory;
• at least one adder circuit included in said arithmetic circuit that receives plural input signals and generates a sum thereof;
• wherein said at least one adder includes a static circuit for generating an arithmetic output, including:
• a first set of P type and N type transistor devices;
• a second set of P type and N type transistor devices, having a second switching characteristic, symmetrically connected to one another such that each said P type transistor has a corresponding N type transistor said first set of devices and said second set of devices being formed on an insulating layer which introduces a floating body effect caused by said insulating layer wherein a varying voltage drop occurs across said first set of devices and said second set of devices such that said output and a complement thereof are provided concurrently on respective output nodes of said circuit;
• wherein each of said P type transistors and said corresponding N type transistors in said first set of devices are concurrently in either a turned on or turned off state and each of said P type transistors and said corresponding N type transistors in said second set of devices are concurrently in either a turned on or turned off state, such that said floating body effect is minimized.

A method of generating an arithmetic output from a static summing circuits, said method comprising the steps of:

• providing a first set of P type and N type transistor devices symmetrically connected to one another such that each said P type transistor has a corresponding N type transistor;
• and
• symmetrically connecting a second set of P type and N type transistor devices, to one another such that each said P type transistor has a corresponding N type transistor wherein said first set of devices and said second set of devices are formed on an insulating layer which introduces a floating body effect caused by said insulating layer wherein a varying voltage drop occurs across said first set of devices and said second set of devices;
• wherein said arithmetic output and a complement thereof are provided concurrently on respective output nodes of said circuit;
• and
• wherein each of said P type transistors and said corresponding N type transistors in said first set of devices are concurrently in either a turned on or turned off state and each of said P type transistors and said corresponding N type transistors in said second set of devices are concurrently in either a turned on or turned off state, such that said floating body effect is minimized.

A static circuit for generating an arithmetic output, comprising:

• a first set of N type transistor devices and P type transistor devices, said N type transistor devices and said P type transistor devices in said first set being symmetrically connected to one another;
• a second set of N type transistor devices and P type transistor devices, said N type transistor devices and said P type transistor devices in said second set being symmetrically connected to one another;
• and
• a third set of N type transistor devices and P type transistor devices, said N type transistor devices and said P type transistor devices in said third set being symmetrically connected to one another;
• wherein all of said N type transistor devices and said P type transistor devices in said first, second and third sets are formed on an insulating layer which introduces a floating body effect caused by said insulating layer wherein a varying voltage drop occurs across said devices in said first, second and third sets;
• wherein the N type transistor devices and P type transistor devices in said first set and said second set are all in one of a turned on state or a turned off state at any given time period and wherein the N type transistor devices and P type transistor devices in said third set are in one of a turned on state or a turned off state respective to one another at any given time period to minimize said floating body effect;
• and
• wherein said arithmetic output and a complement thereof are provided concurrently on respective output nodes of said circuit.