Apparatus and method of performing addition and rounding operation in parallel for floating-point arithmetic logical unit

An apparatus for performing an addition and a rounding operation in parallel for a floating-point arithmetic logical unit (ALU) having an exponent alignment/normalization section for either aligning exponents or normalization, an addition and rounding section for performing a fraction part addition and rounding, the apparatus comprising:

• first and second bit-exclusion-OR (XOR) operators for bypassing or inverting two bit stream output values of the exponent alignment section in accordance with first and second control signals externally inputted;
• a leading zero counter for calculating a leading zero using an output signal of the first bit-XOR operator;
• a multiplexer for selecting and outputting on of an output value of the leading zero counter and a shift amount for exponent alignment obtained through a separate exponent part addition section;
• an alignment right rotator for performing the exponent alignment or the normalization through right or left shifts using an output value of the multiplexer, and producing a guard bit (G), round bit (R), and sticky bit (Sy);
• a bit-half-adder for receiving the two bit streams outputted from the alignment right rotator and the second bit-XOR operator, and outputting a carry and a sum;
• a carry select adder (CA) for outputting a resultant value of addition through the bit-half-adder and a value obtained by adding 1 to the resultant value of addition;
• a multiplexer for selecting and outputting one of two output values of the CSSA in accordance with a fourth control signal externally inputted;
• and
• a correction section for correcting a least significant bit (LSB) of a result of subtraction with respect to an output value of the multiplexer.