Apparatus and method for determining effect of on-chip noise on signal propagation
AssigneeMicron Technology, Inc.
InventorWilliam E. Corr
Life of this patent
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Abstract
The invention relates to an integrated circuit, comprising a core logic area having a plurality of components therein, a first test circuit constructed to mimic a data path within the core logic area, a second test circuit constructed with a plurality of traces routed within the core logic area, a third test circuit constructed with a plurality of elements randomly placed within the core logic area, and a fourth test circuit constructed to mimic a data path within the core logic area, the fourth test circuit sharing a power source with at least one of the plurality of components within the core logic area. Each of the test circuits is operable to produce one or more signals for analyzing the effects of on-chip noise on signal propagation.
Claims9
An integrated circuit, comprising:
- a core logic area having a plurality of components therein;
- a first test circuit constructed to mimic a data path within said core logic area;
- a second test circuit constructed with a plurality of traces routed within said core logic area;
- a third test circuit constructed with a plurality of elements randomly placed within said core logic area;
- and
- a fourth test circuit constructed to mimic a data path within said core logic area, said fourth test circuit sharing a power source with at least one of said plurality of components within said core logic area.
Dependencies are inferred from the claim text.