Rapid defect analysis by placement of tester fail data
AssigneeInternational Business Machines Corporation
InventorsKevin J. Barcomb, Leendert M. Huisman, Kevin C. Quandt
Life of this patent
Estimating the term…
Abstract
A structure and method for identifying a physical location of a defect in a logic circuit based on a physical location of a logic latch having failing data. The logic circuit includes a plurality of logic latches, each having a predetermined physical location within the logic circuit. The logic latches are connected to devices adjacent the logic latches, such that the failing data in the logic latch indicates a failure of a device adjacent the logic latches.
Claims20
A method of locating a physical location of a defect in an integrated circuit chip comprising:
- identifying exact physical locations of logic latches within said integrated circuit chip;
- supplying test signals to said integrated circuit chip, wherein defective portions of said integrated circuit chip produce failing data in said logic latches;
- and
- identifying said physical location of said defect in said integrated circuit chip based on physical locations of said logic latches having failing data.
A method of identifying approximate physical locations of defects in an integrated circuit chip, said method comprising:
- supplying test signals to said integrated circuit chip, wherein defective portions of said integrated circuit chip produce ailing data in logic latches in response to said test signals;
- identifying physical locations of logic lathes that have said failing data;
- and
- identifying approximate locations of defects in said integrated circuit chip as those areas that are adjacent to said logic latches that have said failing data.
A method of identifying approximate physical locations of defects in an integrated circuit chip, said method comprising:
- supplying test signals to said integrated circuit chip, wherein defective portions of said integrated circuit chip produce failing data in logic latches in response to said test signals;
- identifying physical locations of logic latches that have said failing data;
- and
- displaying a map of said physical locations of said logic latch having failing data to graphically identify approximate locations of defects in said integrated circuit chip.
Dependencies are inferred from the claim text.