Optimized high-level data link control encoding/decoding

A method for decoding data in a High level Data Link Control (HDLC) protocol frame comprising the steps of:

• inputting a stream of data having a data width of w-bits into an N-bit register where N>w from a data field in the HDLC frame;
• examining w-bits from the N-bit register and determining a bit count number of bits to transfer to an input buffer;
• deleting a zero if the examined w-bits from the N-bit register indicates to perform a zero delete in accordance with the HDLC protocol;
• inputting the bit count number of bits to an input buffer;
• if the bit count number of bits=w, selecting a next w-bits from the N-bit register to examine, the next w-bits including a w-unexamined bits next to the examined w-bits;
• if the bit count number of bits <w, selecting a next w-bits from the N-bit register to examine, the next w-bits including a number of bits equal to w minus the bit count from the examined w-bits and a number of unexamined bits equal to the bit count from the N-bit register;
• and
• repeating the steps of examining, inputting and selecting.

An improved High level Data Link Control Layer encoder in a data communication system, the improvement comprising:

• an N-bit register, where N>w, the N-bit register being operable to receive up to N data bits from data having a data width of w-bits;
• a register controller coupled to the N-bit register, the register controller being operable to examine a w-bit unit from the N-bit register to determine a zero insert indicator and a bit count from the w-bits to output on a transmission medium, the register controller being operable to select a next w-bits from the N-bit register if the bit count is equal to w and, if a number of examined bits equal to w minus the bit count were not sent, to select the unsent examined bits and a number of unexamined bits equal to the bit count from the N-bit register;
• and
• an output buffer coupled to the N-bit register to receive the bit count number of bits, and, if the zero insert indicator is set, an inserted zero bit, the output buffer being coupled to the transmission medium to output the bits over the transmission medium.

An improved High level Data Link Control Layer decoder in a data communication system, the improvement comprising:

• an N-bit register, where N>w, the N-bit register for receiving up to N data bits from data having a data width w-bits;
• a decoder register controller coupled to the N-bit register, the register controller being operable to examine a w-bit unit from the N-bit register to determine a zero delete indicator and a bit count from the w-bits to transfer to an input buffer, the register controller being operable to select a next w-bits from the N-bit register if the bit count is equal to w and, if a number of examined bits equal to w minus the bit count were not sent, to select the unsent examined bits and a bit count number of unexamined bits from the N-bit register, the decode register controller operable to shift out a zero if the zero delete indicator indicates a zero delete;
• and
• an input buffer coupled to the N-bit register to receive the bit count number of bits, the input buffer being coupled to a receiver buffer.