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US 6,785,290 B1Granted
Line interface integrated circuit and packet switch
AssigneeKabushiki Kaisha Toshiba
InventorsToshio Fujisawa, Toshitada Saito, Jun Hasegawa
Life of this patent
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Abstract
ATM cells inputted into a physical layer interface (12) are once stored in a cell buffer (24) regardless whether they are ATM cells to be outputted from a switching interface (22) or ATM cells addressed to host CPU (26), and the ATM cells addressed to the host CPU are stored in a temporary RAM (18) at a timing controlled by a scheduler (16). The host CPU 26 read out ATM cells stored in the temporary RAM (18) when necessary. Thereby, no FIFO memory is needed to temporarily store ATM cells addressed to the host CPU (26).
Claims20
A line interface integrated circuit having an input-side interface supplied with packets and an output-side interface outputting the packets, comprising:
- a first storage device configured to temporarily store packets toward CPU and be accessed by the CPU when necessary;
- and
- a scheduler configured to classify packets outputted from the input-side interface at least into a first queue for accumulating packets to be outputted from the output-side interface and a second queue for accumulating packets addressed to CPU, and accumulate the packets in a buffer, the scheduler managing the order of outputting the packets accumulated in the queues of the buffer to output the packets accumulated in the first queue to the output-side interface and output the packets accumulated in the second queue to the first storage device.
A packet switch comprising:
- at least one ingress-side physical layer controller connected to a physical layer which is an input side of the packets;
- at least one ingress-side line interface device connected to the ingress-side physical layer controller;
- a routing switch connected to the ingress-side line interface device;
- at least one egress-side line interface device connected to the routing switch;
- and
- at least one egress-side physical layer controller having one side connected to the egress-side line interface device and the other side connected to a physical layer which is the output side of the packets,
- wherein each line interface device of the ingress-side line interface device and the egress-side line interface device comprises:
- an input-side interface supplied with the packets;
- an output-side interface outputting the packets;
- a buffer supplied with packets outputted from the input-side interface and accumulating the packets classified at least into a first queue for accumulating packets to be outputted from the output-side interface and a second queue for accumulating packets addressed to CPU;
- a first storage device configured to temporarily store packets outputted from the buffer toward the CPU and be accessed by the CPU when necessary;
- and
- a scheduler configured to manage the order of outputting the packets accumulated in the queues of the buffer to output the packets accumulated in the first queue to the output-side interface and output the packets accumulated in the second queue to the first storage device.
10 more elements
A line interface integrated circuit having a physical layer interface connected to a physical layer controller to input and output packets, and a switch interface connected to a routing switch to output and input packets, comprising:
- first and second storage devices configured to temporarily store packets toward CPU and be accessed by the CPU when necessary;
- an ingress-side scheduler configured to classify the packets outputted from the physical layer interface at least into a first queue for accumulating packets to be outputted from the switch interface and a second queue for accumulating packets addressed to the CPU, and accumulate the packets in an ingress-side buffer, the ingress-side scheduler managing the order of outputting the packets accumulated in the queues of the ingress-side buffer to output the packets accumulated in the first queue to the switch interface and output the packets accumulated in the second queue to the first storage device;
- and
- an egress-side scheduler configured to classify the packets outputted from the switch interface at least into a third queue for accumulating packets to be outputted from the physical layer interface and a fourth queue for accumulating packets addressed to the CPU, and accumulate the packets in an egress-side buffer, the egress-side scheduler managing the order of outputting the packets accumulated in the queues of the egress-side buffer to output the packets accumulated in the third queue to the physical layer interface and output the packets accumulated in the fourth queue to the second storage device.
1 more element
A packet switch comprising:
- at least one physical layer controller connected to a physical layer;
- at least one line interface device connected to the physical layer controller;
- and
- a routing switch connected to the line interface device,
- wherein the line interface device comprises:
- a physical layer interface connected to the physical layer controller to input and output packets;
- a switch interface connected to the routing switch to output and input packets;
- an ingress-side buffer supplied with the packets outputted from the physical layer interface, and accumulating the packets classified at least into a first queue for accumulating packets to be outputted from the switch interface and a second queue for accumulating packets addressed to CPU;
- a first storage device configured to temporarily store packets outputted from the ingress-side buffer toward the CPU and be accessed by the CPU when necessary;
- an ingress-side scheduler configured to manage the order of outputting the packets accumulated in the queues of the ingress-side buffer to output the packets accumulated in the first queue to the switch interface and output the packets accumulated in the second queue to the first storage device;
- an egress-side buffer supplied with the packets outputted from the switch interface, and accumulating the packets classified at least into a third queue for accumulating packets to be outputted from the physical layer interface and a fourth queue for accumulating packets addressed to the CPU;
- a second storage device configured to temporarily store packets outputted from the egress-side buffer toward the CPU and be accessed by the CPU when necessary;
- and
- an egress-side scheduler configured to manage the order of outputting the packets accumulated in the queues of the egress-side buffer to output the packets accumulated in the third queue to the physical layer interface and output the packets accumulated in the fourth queue to the second storage device.
11 more elements
Dependencies are inferred from the claim text.