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US 6,785,284 B1Granted
Interleavement for transport of frames and cells
AssigneeInfineon Technologies North America Corp.
InventorGunnar Hagen
Life of this patent
Estimating the term…
Abstract
A DMA system includes a plurality of transmit-receive pairs (102, 104) for communicating on a bus. A DMA controller (108) supervises bus handling. The DMA controller (108) includes a priority controller (114), a bus sniffer (112), and a context machine (116). The bus sniffer (112) and context machine (116) identify block transfers as frame or cell transfers and supervise interleaving. The priority controller (114) resolves the priority of each of the constituent transfers of the frame or cell block transfers using a matrix of priority tokens.
Claims15
A direct memory access LDMA) controller, comprising:
- a bus;
- priority resolver adapted to resolve concurrent data transfers on the bus and grant a given data transfer access to the bus on a prereserved basis using tokens, a token having been previously assigned to each data transfer through p configuration interface, each token having a static rank and a dynamic rank, the static rank of a token being based on a position within a matrix of ((m+1)×(n+1)) configuration bits, wherein n represents a number of configuration registers and m represents a size of each of the configuration registers, the dynamic rank of a token being based on a comparison of the static rank of pending concurrent data transfers;
- a bus sniffer adapted to identify a cast type of a granted data transfer on the bus, a cast type being whether a given data transfer on the bus pertains to a frame transfer or a cell transfer, a frame being an Internet Protocol (IP) data packet having an arbitrary length, a cell being an asynchronous transfer mode (ATM) data packet of a fixed length;
- and
- a context machine adapted to store request contexts for data transfers on the bus, and adapted to serve a granted data transfer on the bus based on a context corresponding to the granted data transfer;
- wherein the priority resolver unit is adapted to read a the cast type associated with each granted data transfer and interleave ATM data packets and IP data packets on the bus.
3 more elements
A DMA controller in accordance with claim 4, wherein the bus sniffer is adapted to assert an end of frame signal when a transfer of an IP data packet is complete.
A direct memory access method, comprising:
- resolving concurrent data transfers on a bus and granting a given data transfer access to the bus on a prereserved basis using tokens, a token having been previously assigned to each data transfer through a configuration interface, each token having a static rank and a dynamic rank, the static rank of a token being based on a position within a matrix of ((m+1)×(n+1)) configuration bits, wherein n represents a number of configuration registers and m represents a size of each of the configuration registers from (0, 1, . . . m) the dynamic rank of a token being based on a comparison of the static rank of pending concurrent data transfers;
- identifying a cast type of a granted data transfer on the bus, a cast type being whether a given data transfer on the bus pertains to a frame transfer or a cell transfer, a frame being an Internet Protocol (IP) data packet having an arbitrary length a cell being an asynchronous transfer mode (ATM) data packet of a fixed length;
- storing request contexts for data transfers and serving a granted data transfer based on a context corresponding to the granted data transfer;
- and
- reading a the cast type associated with each granted data transfer and transferring each granted data transfer including interleaving ATM data packets and IP data packets on the bus.
2 more elements
A direct memory access (DMA) controller, comprising:
- means for resolving concurrent data transfers on a bus and granting a given data transfer access to the bus on a prereserved basis using tokens, a token having been previously assigned to each data transfer through a configuration interface, each token having a static rank and a dynamic rank, the static rank of a token being based on a position within a matrix of ((m+1)×(n+1)) configuration bits, wherein n represents a number of configuration registers and m represents a size of each of the configuration registers, the dynamic rank of a token being based on a comparison of the static rank of pending concurrent data transfers;
- means for identifying a cast type of a granted data transfer on the bus, a cast type being whether a given data transfer on the bus pertains to a frame transfer or a cell transfer, a frame being an Internet Protocol (IP) data packet having an arbitrary length, a cell being an asynchronous transfer mode (ATM) data packet of a fixed length;
- means for storing request contexts for data transfers and serving a granted data transfer based on a context corresponding to the granted data transfer;
- and
- means for reading a the cast type associated with each granted data transfer and transferring each granted data transfer including interleaving ATM data packets and IP data packets on the bus.
2 more elements
Dependencies are inferred from the claim text.