Group switching system for multiple-channel data
AssigneeLG Electronics Inc.
InventorJae Uk Eum
Life of this patent
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Abstract
A group switching apparatus for multi-channel data is disclosed. It includes a speech memory to temporarily store a time slot to be switched, and a connection memory (CM) to store group connection information. Also, it includes a processor matching unit to interface group connection information provided from an upper processor to the CM and a counter to count a system clock signal and output a read address for the CM. Additionally, an offset generating unit receives group connection information outputted from the CM and generates a first offset value according to a signal representing an ‘ON’ state of group connection, and an adder adds the output of the counter and the output of the offset generating unit and outputting the added value as a read address for the SM.
Claims32
A group switching apparatus for multiple-channel data, comprising:
- a speech memory (SM) coupled to temporarily store at least one time slot to be switched;
- a connection memory (CM) coupled to store single connection information;
- a group connection memory (GCM) coupled to store group connection information;
- a counter coupled to count a system clock signal and output a read address to the CM;
- an address generator configured to convert an output of the counter and generate a read address for the GCM;
- a processor matching unit configured to provide interfacing connection information received from an upper processor to one of the CM and GCM;
- a multiplexer coupled to selectively output an output of the CM or an output of the GCM according to a connection state signal outputted from the GCM;
- and
- an adder coupled to add an output of the counter and the output of the multiplexer, and output an added value as a read address for the SM.
A group switching apparatus for multiple-channel data, comprising:
- a speech memory (SM) coupled to temporarily store a time slot to be switched;
- a connection memory (CM) coupled to store group connection information;
- a processor matching unit configured to interface the CM to group connection information received from an upper processor;
- a counter coupled to count a system clock signal and output a read address for the CM;
- an offset generator coupled to receive the group connection information outputted from the CM and generate a first offset value according to a state signal of a group connection;
- and
- an adder coupled to add an output of the counter and the output of the offset generating unit and output the added value as a read address for the SM.
A multiple channel time switch, comprising:
- a memory device coupled to receive input data in at least one time slot;
- a counter coupled to receive a system clock signal and output a read address signal;
- a connection memory coupled to receive the read address signal, a state signal, and connection information to generate offset information;
- and
- an offset circuit coupled to selectively output a first output of the connection memory and a second output of the connection memory in response to a control signal, and add the selected output to the output of the counter to generate an offset signal to switch the time slot of the input data.
A multiple channel time switch, comprising:
- a memory device coupled to receive input data for at least one time slot;
- a counter coupled to receive a system clock signal and output a read address signal;
- a connection memory coupled to receive the read address signal, a state signal, and connection information to generate offset information;
- a loadable down counter (LDC) configured to load a group connection number when the state signal is ‘1’, and count down from the group connection number in accordance with the system clock signal;
- a comparator configured to determine whether the count value of the LDC is equal to a reference value;
- a logic gate to logically combine an output of the comparator and the system clock signal;
- a latch configured to output one of a first and second output of the connection memory as an offset value according to a latch clock signal outputted from the logic gate.
Dependencies are inferred from the claim text.