Method and apparatus for improving noise immunity in a DDR SDRAM system

A memory controller adapted for use on a printed circuit board (“PCB”) with a double data rate synchronous dynamic random access memory (“DDR SDRAM”), the memory controller comprising:

• control circuits to provide to the DDR SDRAM, during a READ operation, a clock signal, and to receive from the DDR SDRAM, during said READ operation, a DQS signal;
• and
• DQS qualifying circuits to frame the DQS signal for a predetermined portion of the READ operation to generate a framed DOS signal, the DOS qualifying circuits including
• a DQSQ frame generator circuit that, in response to an assertion of a read burst signal from the control circuits, provides a DOS Qualifier signal that is delayed from the assertion of the read burst signal by an amount of time based on a CAS latency signal,
• wherein the DOS Qualifier signal is provided from the memory controller to an input to a path on the PCB and then received by the memory controller from an output of the path on the PCB as a further delayed DOS qualifier signal,
• the memory controller further including circuitry to couple the output of the path on the PCB to the control circuits, to provide the further delayed DOS qualifier signal to the control circuits for generating the framed DOS signal.