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US 6,785,184 B2Granted
Self-timed activation logic for memory
AssigneeIntel Corporation
InventorsThu V. Nguyen, Ruban Kanapathippillai
Life of this patent
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Abstract
A self timed logic circuit is used to generate a self timed memory clock to access data in a memory. The self timed memory clock has a periodic pulse which enables circuitry in the memory for a brief period of time over its pulse width. The amount of charge and voltage change, required on bit lines for resolving a bit of data stored in a memory cell during the pulse width of the self timed memory clock, is reduced by using a sensitive sense amplifier so that power can be conserved.
Claims16
A method comprising:
- generating a self timed memory clock including periodic pulses;
- selectively enabling an array of sense amplifiers coupled to bit lines of a memory in response to a narrow pule width of the periodic pulses;
- and
- selectively determining a logical state of memory cells coupled to the bit lines in response to the narrow pulse width of the periodic pulses.
1 more element
An apparatus comprising:
- a delay to generate delayed inverted clock signal based on a clock input signal;
- a first NAND gate receive and NAND together the delayed inverted clock signal and the clock input signal and to generate an inverted first memory clock signal including a narrow periodic pulse;
- a first inverter to receive and invert the inverted first memory clock signal and to generate a second memory lock signal including a narrow periodic pulse;
- a second NAND gate to receive and NAND together the second memory clock signal and a memory enable signal, the second NAND gate to generate a third memory clock signal;
- and
- a second inverter to receive and invert the third memory clock signal to generate a fourth memory clock signal including a narrow pulse width.
3 more elements
A memory comprising:
- a memory array including a plurality of memory cells arranged into rows and columns;
- a self timed logic circuit to generate a self timed memory clock signal including a narrow periodic pulse;
- a row address decoder coupled to receive the self timed memory clock signal, the row address decoder to selectively generate a word line signal to access a row of memory cells in response to the narrow periodic pulse of the self timed memory clock signal;
- and
- an array of sense amplifiers coupled to bit lines of the columns of memory cells in the memory array, the sense amplifiers to determine a logical level stored in the memory cells that are addressed by the row address decoder, each sense amplifier to receive the self timed memory clock signal to enable differentiation between a voltage levels on a negative bit line and a positive bit line, each sense amplifier to determine the logical level stored in the memory cells during the narrow periodic pulse.
2 more elements
Dependencies are inferred from the claim text.