Semiconductor memory device and electronic instrument

A semiconductor memory device comprising:

• a plurality of word lines extending along a first direction;
• a plurality of memory cells to be selected by each of the word lines, the memory cells being disposed along the first direction and a second direction, the first and second directions intersecting each other;
• a plurality of sub power source lines extending along the first direction, each of the sub power source lines supplying a power source voltage to the memory cells arranged along the first direction;
• a main power source line supplying the power source voltage to the sub power source lines;
• and
• a plurality of fuse elements connecting the main power source line to the sub power source lines,
• wherein a predetermined number of the sub power source lines are connected by one of a plurality of common connecting sections, each of the common connecting sections being provided at one end of the predetermined number of the sub power source lines and being connected to the main power source line through each of the fuse elements,
• wherein the word lines have a plurality of main word lines and a plurality of sub word liner, the sub word lines being subordinate to each of the main word lines, each of the sub word lines being connected to the memory cells arranged in the first direction, and
• wherein the number of the predetermined number of the sub power source lines commonly connected to each of tho common connecting sections is equal to the number of the sub word lines subordinate to each of the main word lines.

A semiconductor memory device comprising:

• a plurality of word lines extending along a first direction;
• a plurality of memory cells to be selected by each of the word lines, the memory cell being disposed along the first direction and a second direction, the first and second directions intersecting each other;
• a plurality of sub power source lines extending along the first direction, each of the sub power source lines supplying a power source voltage to the memory cells arranged along the first direction;
• a main power source line supplying the power source voltage to the sub power source lines;
• and
• a plurality of fuse elements connecting the main power source line to the sub power source lines,
• wherein a predetermined number of the sub power source lines are connected by one of a plurality of common connecting sections, each of the common connecting sections being provided at one end of the predetermined number of the sub power source lines and being connected to the main power source line through each of the fuse elements.
• wherein each of the sub power source lines includes a first sub power source line and a second sub power source line, the first sub power source line being located below the second sub power source line, an interlayer dielectric being formed between the first and second sub power source lines,
• wherein the second sub power source line is formed of a metal layer and connected to each of the common connecting sections,
• wherein the first sub power source line is formed of a layer having higher resistance than the second sub power source line and connected to the memory cells arranged along the first direction, and
• wherein the first sub power source line is connected to the second sub power source line through a via.

A semiconductor memory device comprising:

• a plurality of word lines extending along a first direction;
• a plurality of memory cells to be selected by each of the word lines, the memory cells being disposed along the first direction and a second direction, the first and second directions intersecting each other;
• a plurality of sub power source lines extending along the first direction, each of the sub power source lines supplying a power source voltage to the memory cells arranged along the first direction;
• means for supplying the power source voltage to the sub power source lines;
• and
• a plurality of fuse elements connecting the means for supplying the power source voltage to the sub power source lines,
• wherein a predetermined number of the sub power source lines are connected by one of a plurality of common connecting sections, each of the common connecting sections being provided at one end of the predetermined number of the sub power source lines and being connected to the means for supplying the power source voltage through each of the fuse elements;
• wherein the word lines have a plurality of main word lines and a plurality of sub word lines, the sub word lines being subordinate to each of the main word lines, each of the sub word lines being connected to the memory cells arranged in the first direction, and
• wherein the number of the predetermined number of the sub power source lines commonly connected to each of the common connecting sections is equal to the number of the sub word lines subordinate to each of the main word lines.

A method for preventing leakage current in a semiconductory memory device comprising:

• extending a plurality of word lines in a first direction;
• selecting plurality of memory cells by each of the word lines;
• disposing the memory cells along the first direction, and a second direction, wherein the first and second directions intersect each other;
• extending a plurality of sub power source lines along the first direction,
• supplying a power source voltage to the memory cells arranged along the first direction;
• supplying the power source voltage to the sub power source lines;
• and
• connecting the main power source line to the sub power source lines by a plurality of fuse elements;
• connecting one of a plurality of common connecting sections, by a predetermined number of sub power source lines;
• providing at one end of the predetermined number of the sub power source lines each of the common connecting sections;
• and connecting each of the common connecting sections to the main power source line through each of the fuse elements;
• providing a plurality of main word lines and a plurality of sub word lines, the sub word lines being subordinate to each of the main word lines,
• connecting each of the sub word lines to the memory cells arranged in the first direction,
• wherein the number of the predetermined number of the sub power source lines commonly connected to each of the common connecting sections is equal to the number of the sub word lines subordinate to each of the main word lines.