Method of accessing memory and device thereof
AssigneeFreescale Semiconductor, Inc.
InventorsJon S. Choy, Bruce L. Morton
Life of this patent
Estimating the term…
Abstract
A memory device is disclosed having a column select transistor gate that is controlled by tri-statable control logic. The tri-statable control logic operates to allow the gate of the column select transistor to float during sensing of the bit cell. The column select transistor acts as a floating gate amplifier, i.e. a common gate amplifier having a gate that floats during the sensing period. In addition, the column select transistor can operate to facilitate decoding of the memory and to allow precharge of a bit line of a memory cell. Further, avoidance of a static power drain is made possible by the fact that the gate is floating during the sensing period.
Claims21
A memory device having a decode path, comprising:
- a flash memory cell having a flash cell first current electrode, a flash cell second current electrode, and a flash cell control electrode;
- a set of column select transistors, including at least one column select transistor having a column select transistor first current electrode connected to the flash cell first current electrode, a column select transistor second current electrode, and at least one column select transistor control electrode;
- a tri-statable control logic coupled to the column select transistor control electrode;
- and
- a precharge transistor having a precharge transistor first current electrode coupled to the at least one column select transistor second current electrode, a precharge transistor second current electrode, and a precharge transistor select electrode.
A memory device having a decode path, comprising:
- an SRAM (Static Random Access Memory) memory cell having an SRAM cell first current electrode, an SRAM cell second current electrode, and an SRAM cell control electrode;
- a set of column select transistors, including at least one column select transistor having a column select transistor first current electrode connected to the SRAM cell first current electrode, a column select transistor second current electrode, and at least one column select transistor control electrode;
- a tri-statable control logic coupled to the column select transistor control electrode;
- and
- a precharge transistor having a precharge transistor first current electrode coupled to the at least one column select transistor second current electrode, a precharge transistor second current electrode, and a precharge transistor select electrode.
A device comprising:
- a non-volatile memory (NVM) cell having a NVM first current electrode and a NVM second current electrode;
- a column select transistor having a column select transistor first transistor current electrode coupled to the NVM second current electrode and a column select transistor gate;
- and
- a tri-statable control module having a tri-statable output coupled to the column select transistor gate.
A method of operating a non-volatile memory device, the method comprising:
- providing a bias voltage to a control gate of a transistor to facilitate charging a bit line of a non-volatile cell;
- electrically isolating the control gate of the transistor after providing the bias voltage to allow the control gate to float;
- sensing a current through the transistor to determine a state of the non-volatile cell when the control gate of the transistor is floating.
A method comprising:
- applying an address to select a memory cell of a memory, the memory cell supplied by a supply reference voltage;
- enabling a transistor to apply a charge to a bit line coupled to the memory cell during a first time period;
- and
- capacitively coupling a control gate of the transistor to the supply reference voltage during a second time period.
A device comprising:
- a memory having a plurality of memory cells, the plurality of memory cells supplied by a supply reference voltage;
- address selection logic to apply an address to select at least one memory cell of the plurality of memory cells;
- a pre-charge element to provide a charge to charge a bit line corresponding to the at least one memory cell;
- and
- a single transistor coupled to the bit line, the single transistor is to allow the bit line to charge during a first time period, and is to operate as a floating gate amplifier during a second time period, where a gate of the single transistor is to float with respect to the supply reference voltage.
Dependencies are inferred from the claim text.