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US 6,785,175 B2Granted
Method for repairing memory cell
AssigneeNanya Technology Corporation
InventorsChin-Min Chang, Yu-Lin Shen, Cheng-Cheng Wu
Life of this patent
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Abstract
A method for repairing a memory cell having a plurality of bit lines. The memory cell is tested with a compression testing mode, and future testing is set to compression testing mode when an error is detected, or to normal testing mode when no error is detected. It is determined whether detected errors warrant repair, and all repairs deemed necessary are performed.
Claims11
A method for repairing a memory cell, wherein the memory cell has a plurality of bit lines, comprising:
- providing a memory cell;
- testing the memory cell with a compression testing mode;
- setting future testing of subsequent cells to compression testing mode when an error is detected or to normal testing mode when no error is detected;
- testing the memory cell with a normal testing mode;
- determining whether detected errors on the memory cell are warranted;
- and
- performing any repairs deemed necessary.
4 more elements
A method for repairing a memory cell, comprising:
- providing a memory cell, wherein the memory cell has a plurality of regular bit lines;
- separating the regular bit lines into groups of N strips;
- testing each group of regular bit lines with a compression testing mode;
- setting future tests of subsequent groups to compression testing mode when errors are detected or to normal testing mode when no errors are detected;
- recording errors in the regular bit lines;
- testing each group of regular bit lines with a normal testing mode;
- recording any newly detected errors;
- determining whether repair of detected errors is warranted;
- and
- performing any repairs deemed necessary.
7 more elements
Dependencies are inferred from the claim text.