Testing method and device for non-volatile memories having a LPC (low pin count) communication serial interface

A memory device comprising:

• a serial interface;
• an array of memory cells connected to said serial interface;
• an address storage block;
• a first address bus connected between said array of memory cells and said address storage block;
• a bank of registers to be addressed and accessed in a test mode for serially loading test data therein;
• and
• a first switch for connecting said bank of registers to said first address bus.

A method of testing a non-volatile memory device comprising a serial interface having a low pin count, an array of memory cells connected to the serial interface, and a bank of registers connected to the array of memory cells, the method comprising:

• activating a test mode of the non-volatile memory device via an address storage block by generating a test mode signal, the address storage block being connected to the bank of registers and the array of memory cells via a first address bus;
• enabling the bank of registers to serially receive a predetermined data set via an input bus connected to the serial interface;
• and
• loading test data into the bank of registers via a serial communication protocol.