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US 6,785,173 B2Granted
Semiconductor memory device capable of performing high-frequency wafer test operation
AssigneeSamsung Electronics Co., Ltd.
InventorsKwon-Il Sohn, Uk-Rae Cho, Kwang-Jin Lee
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Abstract
A semiconductor memory device generates a test clock signal (whose periods and cycle number are variable) having a shorter cycle than that of an external clock signal, and internally test data using the test clock signal. The semiconductor memory device may repeatedly perform read/write operations using the internally generated test clock signal during a half cycle of the external clock signal. By comparing output data in the read operation with known data, a test apparatus may determine whether memory cells of a memory device are normal. In a low-frequency test apparatus, it is possible to screen disadvantages that may occur when a high-speed memory device operates at a high frequency.
Claims28
A semiconductor memory device comprising:
- a memory cell array for storing data information;
- an address buffer circuit for receiving an external address in response to a test clock signal;
- means for generating a test period signal synchronized with an external clock signal in a test operation mode;
- means for generating a test clock signal in response to the test period signal during a half cycle of the external clock signal, the test clock signal having a shorter cycle than that of the external clock signal;
- means for generating test data in response to the test clock signal;
- means for writing the test data in an area of the memory cell array addressed by the external address in each cycle of the test clock signal;
- means for reading the test data from the area of the memory cell array in each cycle of the test clock signal and outputting the read-out data to data lines;
- and
- means for receiving data bits on the data lines and determining whether the data bits thereon have the same value,
- wherein the means for receiving the data bits outputs an external flag signal as a determination result.
7 more elements
A semiconductor memory device comprising:
- a memory cell array for storing data information;
- an address buffer circuit for receiving an external address in response to a test clock signal;
- a clock buffer circuit, operating in response to a wafer test flag signal, for generating a test period signal in a wafer test operation mode in response to an external clock signal;
- a test clock generation circuit for generating a test clock signal in response to the test period signal during a half period of the external clock signal, the test clock signal having a shorter period than that of the external clock signal;
- a test clock control circuit for determining whether a cycle number of the test clock signal is equal to a reference cycle number and allowing the test clock generation circuit to stop generation of the test clock signal, the test clock control circuit generating test data to be written in the memory cell array;
- a write circuit for writing the test data in an area of the memory cell array addressed by the external address in each cycle of the test clock signal;
- a read circuit for reading the test data from the area of the memory cell array in each cycle of the test clock signal and outputting the read-out test data to data lines;
- a first latch pulse generation circuit for generating first and second latch pulse signals in response to the external clock signal;
- a second latch pulse generation circuit for generating a third latch pulse signal in response to a signal on one of the data lines;
- and
- a comparator circuit, operating in response to the first to third latch pulse signals, for determining whether data bits on the data lines have the same value and externally outputting a flag signal as a determination result.
8 more elements
A semiconductor memory device comprising:
- means for generating a test period signal synchronized with an external clock signal;
- means for generating a test clock signal in response to the test period signal during a half cycle of the external clock signal, the test clock signal having a shorter cycle than that of the external clock signal;
- means for generating test data in response to the test clock signal;
- means for writing the test data in an area of a memory cell array in each cycle of the test clock signal and/or reading the test data from the area of the memory cell array in each cycle of the test clock signal.
1 more element
A semiconductor memory device comprising:
- a clock buffer circuit, for generating a test period signal in a wafer test operation mode in response to an external clock signal;
- a test clock generation circuit for generating a test clock signal in response to the test period signal during a half period of the external clock signal, the test clock signal having a shorter period than that of the external clock signal, wherein the test clock generation circuit may stop generation of the test clock signal;
- a test clock control circuit for determining whether a cycle number of the test clock signal is equal to a reference cycle number, the test clock control circuit generating test data to be written in a memory cell array;
- a read/write circuit for writing the test data in an area of the memory cell array in each cycle of the test clock signal and/or reading the test data from the area of the memory cell array in each cycle of the test clock signal.
1 more element
Dependencies are inferred from the claim text.