US 6,785,172 B2 · Semiconductor memory device

Abstract

In a semiconductor memory device according to the present invention, which allows a memory cell array unit and a memory circuit internal logic unit to be tested independently of each other, a first test circuit unit TCi1 to which an address signal a″, a scan-in signal SIN, a scan select signal SS and a shift clock signal SCLK are input, outputs an address signal a′″ and a scan-out signal SiOUT1. The address signal a′″ is input to the memory cell array unit MCA and a column selector CS, whereas the scan-out signal SiOUT1 is input to a second test circuit unit TCi2. The second test circuit unit TCi2, to which the scan-out signal SiOUT1, the scan select signal SS, a write control signal WCTRL and a scan clock signal SCLK are input, outputs at a scan-out signal SOUT. The first test circuit unit and the second test circuit unit each achieve a parallel/serial conversion function.

Claims20

Dependent claims

A semiconductor memory device comprising:

a memory cell array unit constituted of a plurality of memory cells in which data are stored;
an address signal generating unit that generates an address signal with an n-bit width to specify one or a plurality of memory cells among said plurality of memory cells;
and
an address signal test circuit unit that converts the address signal with the n-bit width output from the address signal generating unit to a serial signal for address signal observation and outputs the serial signal resulting from the conversion.

1 more element

A semiconductor memory device comprising:

a memory cell array unit constituted of a plurality of memory cells in which data are stored;
an address signal generating unit that generates an address signal with an n-bit width to specify one or a plurality of memory cells among said plurality of memory cells;
a data input/output unit outputting data with an m-bit width to be written into said memory cell array unit and the data input/output unit reading out data with the m-bit width from said memory cell array unit;
an address signal test circuit unit converting the address signal with the n-bit width output from the address signal generating unit to a serial signal for address signal observation and outputting the serial signal resulting from the conversion, the address signal test circuit unit converting a test address serial signal provided from the outside to a test address signal with the n-bit width and the address signal test circuit unit taking in the address signal from the address signal generating unit and providing either the test address signal or the address signal to said memory cell array unit;
and
a data test circuit unit converting the data with the m-bit width read out from said memory cell array unit to a serial signal for data observation and outputting the serial signal resulting from the conversion, the data test circuit unit converting a test data serial signal provided from the outside to a test data signal with the m-bit width and the data test circuit unit providing the test data signal to either said memory cell array unit or said data input/output unit.

3 more elements

Dependencies are inferred from the claim text.

Semiconductor memory device

Life of this patent

Semiconductor memory device

Life of this patent

Abstract

Claims20