Data memory with short memory access time
AssigneeInfineon Technologies AG
InventorsSteffen Paul, Volker Schöber
Life of this patent
Estimating the term…
Abstract
A data memory including a main data memory having a plurality of data memory units, a redundancy data memory that includes a plurality of redundancy data memory units for the replacement of defective data memory units of the main data memory, and a redundancy control logic for controlling the access to the redundancy data memory, the main data memory and the redundancy data memory being connected to a data bus in parallel with one another via data lines, and the main data memory and the redundancy control logic being connected, in parallel with one another, via address lines, to an address bus for the addressing of data memory units in the data memory.
Claims14
A data memory, comprising:
- a main data memory having a plurality of data memory units;
- a redundancy data memory comprising a plurality of redundancy data memory units to replace defective data memory units of the main data memory and a redundancy control logic for controlling access to the redundancy data memory, wherein the main data memory and the redundancy data memory are connected to a data bus in parallel with one another via data lines, and wherein the main data memory and the redundancy control logic are connected, in parallel with one another, via address lines, to an address bus for the addressing of data memory units in the data memory.
Dependencies are inferred from the claim text.