Memory cell error recovery

A memory arrangement comprising:

• a first memory cell and a mirror memory cell, each of the memory cells being adapted to receive and store the same bit in response to a write operation and at least one of the memory cells being more susceptible to a bit error in which the stored bit changes from a first state to a second state than to a bit error in which the stored bit changes from the second state into the first state;
• and
• a sense amplifier electrically coupled to the first and mirror memory cells and adapted to provide an output of a “0” in response to a read current from the memory cells being less than the read current corresponding to a single bit when the cell is on and to provide an output of a “1” when said read current is greater than or equal to the read current corresponding to a single bit when the cell is on.

A semiconductor memory array comprising a plurality of memory cell arrangements and adapted for read and write access, each of the plurality of memory cell arrangements comprising:

• a first memory cell and a mirror memory cell, each of the memory cells being adapted to receive and store the same bit in response to a write operation and at least one of the memory cells being more susceptible to a bit error in which the stored bit changes from a first state to a second state than to a bit error in which the stored bit changes from the second state into the first state;
• and
• sense amplifier electrically coupled to the first and mirror memory cells and adapted to provide an output of a “0” in response to a read current from the memory cells being less than the read current corresponding to approximately twice a read current corresponding to a single bit when the cell is on and to provide an output of a “1” when said read current is equal to approximately twice a read current corresponding to a single bit when the cell is on.

A semiconductor memory array comprising a plurality of memory cell arrangements and adapted for read and write access, each of the plurality of memory cell arrangements comprising:

• a first memory cell and a mirror memory cell, each of the memory cells being adapted to receive and store the same bit in response to a write operation and at least one of the memory cells being more susceptible to a bit error in which the stored bit changes from a first state to a second state than to a bit error in which the stored bit changes from the second state into the first state;
• and
• a sense amplifier electrically coupled to the first and mirror memory cells and adapted to provide an output of a “0” in response to a read current from the memory cells being less than a read current corresponding to a single bit when the cell is on and to provide an output of a “1” when said read current is greater than or equal to a read current corresponding to a single bit when the cell is on.