Semiconductor memory device having advanced prefetch block
AssigneeHynix Semiconductor Inc.
InventorYoung-Jin Yoon
Life of this patent
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Abstract
A semiconductor memory device includes an advanced prefetching block for prefetching more bit data at once and effectively arranging the prefetched data so as to reduce an address access time of the semiconductor memory device. The semiconductor memory device having four pipelining latches for prefetching 4-bit data outputted from at least one bank in response to a start address of the 4-bit data and control signals includes a first data multiplexing unit, a second data multiplexing unit, a third order multiplexing unit and a forth order multiplexing unit.
Claims18
A semiconductor memory device having four pipelining latches for prefetching 4-bit data outputted from at least one bank in response to a start address of the 4-bit data and control signals, comprising:
- a first data multiplexing means for receiving a first even datum from a first even line and a first odd datum from a first odd line and determining a data path of each of the first even and odd data between first & second data paths according to a data assigning control signal and outputting a first datum through the first data path and outputting a second datum through the second data path;
- a second data multiplexing means for receiving a second even datum from a second even line and a second odd datum from a second odd line and determining a data path of each of the second even and odd data between third & fourth data paths according to the data assigning control signal and outputting a third datum through the third data path and outputting a fourth datum through the fourth data path;
- a third order multiplexing means for receiving the first datum from the first data path and the third datum from the third data path and sequentially outputting the first and the third data at a rising edge of a first control signal in response to the start address of the inputted data;
- and
- a fourth order multiplexing means for receiving the second datum from the second data path and the fourth datum from the fourth data path and sequentially outputting the second and fourth data to a falling edge of a second control signal in response to the start address of the inputted data,
- wherein the 4-bit data is split into the first even data, the first odd data, the second even data and the second odd data, and the data assigning control signal is used for arranging the inputted data into a data path according to whether the start address of the inputted data is an even number or an odd number.
A semiconductor memory device for prefetching 4-bit data from at least one bank in response to an instruction for reading data, comprising:
- a first control signal generating means for generating a first and a second control signals generated by logically combining a data input control signal with a data output control signal;
- a second control signal generating means for generating a third control signal and a fourth control signal, the third control signal generated by logically combining an odd enable signal which is used for outputting an odd times data with an odd arranging signal which is used for arranging the odd times data in response to a start address of the 4-bit data, the fourth controls signal generated by logically combining an even enable signal which is used for outputting an even times data with a even arranging signal which is used for arranging the even times data in response to a start address of the 4-bit data;
- and
- a signal delivering means controlled by the first, the second and the third control signals for outputting the 4-bit data to a first and a second even data output lines and a first and a second odd data output lines.
Dependencies are inferred from the claim text.