ROM embedded DRAM with programming
AssigneeMicron Technology, Inc.
InventorsCasey Kurth, Scott Derner, Phillip G. Wald
Life of this patent
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Abstract
Programming efficiency of a read only memory (ROM) embedded dynamic random access memory (DRAM) is improved by programming only one polarity of bits in non-volatile cells of the ROM embedded DRAM, and then blanket programming volatile cells in the ROM embedded DRAM to represent the remaining bits.
Claims37
A ROM embedded DRAM, comprising:
- a memory array comprising at least a first portion of ROM cells and a second portion of DRAM cells;
- wherein the ROM cells comprise a plurality of DRAM cells bard shorted to one ROM bit polarity, and a plurality of regular DRAM cells programmable to an opposite ROM bit polarity.
A ROM embedded DRAM, comprising:
- a DRAM array having a first subarray containing non-volatile bits and a second subarray having volatile bits;
- wherein the non-volatile bits of a first polarity are hard shorted to a first non-volatile bit polarity, and wherein the volatile bits of a second, complementary polarity are dynamically programmable as volatile cells to the second polarity.
A method of programming ROM cells of a ROM embedded DRAM, comprising:
- programming in a non-volatile fashion all ROM cells of one polarity to a first data state;
- and
- programming in a volatile fashion all remaining ROM cells to an opposite data state.
A method of fabricating a ROM embedded DRAM, comprising:
- forming a DRAM array;
- and
- forming non-volatile shorts for specific ROM cells in the DRAM array.
A method of operating a ROM embedded DRAM, comprising:
- programming all volatile bits of a ROM section of a ROM embedded DRAM with an opposite polarity logic level from a plurality of hard shorted non-volatile bits in the ROM section.
A method of operating a ROM embedded DRAM, comprising:
- programming in a non-volatile manner a plurality of cells in a ROM portion of the ROM embedded DRAM to a first polarity;
- and
- programming in a volatile programming manner the remaining cells in the ROM portion of the ROM embedded DRAM to a second polarity logically opposite to the first polarity.
A method of programming a ROM portion having a plurality of ROM programmable DRAM cells in a ROM embedded DRAM, comprising:
- hard shorting ROM cells of a first polarity to a potential corresponding to the first polarity;
- isolating fully hard shorted rows of ROM cells;
- and
- programming the remaining ROM cells to a second polarity with the hard shorted ROM cell rows isolated.
A method of initializing a ROM portion of a ROM embedded DRAM comprising:
- hard programming in the ROM section all non-volatile cells of a particular polarity;
- and
- programming remaining volatile cells in the ROM portion of the ROM embedded DRAM to the opposite polarity of the hard programmed non-volatile cells.
A dynamic read only memory (DROM) comprising:
- first memory cells programmed in a non-volatile manner to a first data state;
- and
- second memory cells volatilely programmed to a second data state, wherein the second memory cells comprise capacitors.
A dynamic read only memory (DROM), comprising:
- first memory cells programmed in a non-volatile manner to a first data state;
- second memory cells dynamically programmed to a second data state, wherein the second memory cells comprise capacitors;
- a plurality of bit lines selectively coupleable to either the first or the second memory cells;
- sense amplifier circuitry coupled to the bit lines;
- and
- program circuitry to dynamically program the second memory cells.
A memory, comprising:
- a RAM array of memory cell capacitors;
- and
- a ROM array comprising:
- first memory cells programmed in a non-volatile manner to a first data state;
- and
- second memory cells dynamically programmed to a second data state, wherein the second memory cells comprise capacitors.
A processing system, comprising:
- a processor;
- and
- a memory coupled to the processor to dynamically store data provided by the processor and to provide non-volatile data to the processor, the memory comprising:
- first memory cells programmed in a non-volatile manner to a first data state;
- and
- second memory cells dynamically programmed to a second data state, wherein the second memory cells comprise capacitors.
A processing system, comprising:
- a processor;
- and
- a memory coupled to the processor to dynamically store data provided by the processor and to provide non-volatile data to the processor, the memory comprising:
- a RAM array of memory cell capacitors;
- and
- a ROM array comprising
- first ROM array memory cells programmed in a non-volatile manner to a first data state;
- second ROM array memory cells dynamically programmed to a second data state, wherein the second memory cells comprise capacitors;
- a plurality of bit lines selectively coupleable to either the first or the second ROM array memory cells or both;
- sense amplifier circuitry coupled to the bit lines;
- and
- program circuitry to dynamically program the second ROM array memory cells.
A method, comprising:
- non-volatilely programming first memory cells to a ground voltage;
- and
- dynamically programming second memory cells by storing a charge on a capacitor of the second memory cells.
Dependencies are inferred from the claim text.