Non-volatile semiconductor memory device and data programming method

#The present invention relates to a non-volatile semiconductor memory device and its data programming method.

#A memory cell of an NAND type EEPROM is shown in FIG. 28. FIG. 28 is a schematic sectional view of the memory cell MC. The gate insulation film GO which is formed between floating gate FG and channel region CA is sufficiently thin to allow an electron tunnel effect to occur between the floating gate FG and the channel region CA. Electrons are emitted from the floating gate FG to the channel region CA by supplying a high voltage to the substrate Sb, and 0V to the control gate CG, so that one of a binary data is stored in the memory cell. On the other hand, when the other of a binary data is stored in the memory cell, electron are injected from the channel region CA to the floating gate FG. In order to inject electrons to the floating gate FG, a high voltage is supplied to the control gate CG, and 0V is supplied to the channel region CA, source S and drain D. A part of a memory cell array of the NAND type EEPROM is shown in FIG. 29(a). The memory cells MC are serially connected between the select transistor ST and the transistor 10. Further, FIG. 29(b) shown voltage waveform diagrams at the respective nodes shown in FIG. 29(a). When data are programmed to the memory cells MC, first electrons are emitted from the floating gates FG of all the memory cells MC to the substrate by setting all the row lines WL1 to WLn connected to the control gates CG to 0 V and the substrate to a high voltage. After that, a high voltage is supplied to the row select line S connected to the gates of the select transistors ST connected to the memory cells MC to which data are to be written. At the same time, signal φ which is applied to the gates of the transistors 10 is get to 0 V to turn off transistors 10 to disconnect the memory cells MC from the reference potential VSS. When electrons are injected to the floating gates FG of the memory cells MC, the row line WL corresponding thereto is set to the high potential V1, and column lines D corresponding thereto are set to 0 V. At this time, a potential difference between the floating gates FG and the channel region CA become large enough to occur the electron tunnel effect, so electrons are injected to the floating gates FG from the channel region CA. On the other hand, the non-selected row lines WL are set to the potential V2 lower than the high potential V1. At this time, although the potential of the column lines D is 0 V, since the potential V2 is low, the potential difference between the floating gates FG of the memory cells applied the potential V2 and the channel region CA is not large enough to cause the electron tunnel effect, so electrons are not injected to the floating gates FG of the memory cells applied the potential V2. In the memory cells connected to the line WL of the high potential V1, if the column lines D are set to the potential V3, since the potential difference between the floating gates FG and the channel region CA is not large enough to cause the electron tunnel effect, electrons are not injected to the floating gates FG. In FIG. 29(b), at time T1, electrons are injected to the floating gate FG of memory cell 2n, but not injected into the floating gate FG of the memory cell 1n because the voltage of the column line D1 is the potential V3. In the same way, at time T2, electrons are injected to the floating gate FG of memory cell 11, but not injected to the floating gate FG of the memory cell 21.

#In the memory cells MC, if the electrons are injected to the floating gate FG thereof, the threshold voltage thereof becomes a positive value; and if the electrons are emitted from the floating gate FG thereof, the threshold voltage thereof becomes a negative value. In a data read node, when the memory cell MC is selected, the gate thereof is set to a logic “0”, for instance to 0 V. When the threshold voltage of the selected memory cell MC is the negative value, the selected memory cell MC is turned on. However, when the threshold voltage of the selected memory cell MC is the positive value, the selected memory cell MC in turned off. The data stored in the selected memory cell MC is detected depending on whether or not the selected memory cell MC is turned on. On the other hand, the gate of the non-selected memory cell MC connected to the selected memory cell is set to a logic “1”, for instance to 5 V. So the non-selected memory cell MC is turned on even when electrons are injected into the floating gate.

#FIG. 1 is a circuit diagram showing the essential portion of an embodiment of the first aspect of the present invention;

#FIG. 2 is a table showing various modes of the circuit shown in FIG. 1;

#FIG. 3 is a semiconductor memory device configured with the use of the circuits shown in FIG. 1;

#A first embodiment of the first aspect of the present invention will be described hereinbelow with reference to the drawings. FIG. 1 is a circuit in which a bit checking transistor CT whose conduction state is controlled by signal C in connected between the select transistor ST and the memory cell M1. The bit checking transistor stores whether a memory cell having a negative threshold voltage, which is included the other memory block which is different from the memory block including this bit checking transistor, corresponds to a logic “0” or a logic “1”. In each of the memory blocks, the memory cell having the negative threshold voltage corresponds to a logic “1” and the memory cell having the positive threshold voltage corresponds to a logic “0” if the number of the data of a logic “1” are larger than the number of the data of a logic “0”, on the other hand, the memory cell having the negative threshold voltage corresponds to a logic “0” and the memory cell having the positive threshold voltage corresponds to a logic “1” if the number of the data of a logic “0” are larger than the number of the data of a logic “1”. That is, for each memory cell block 111, the data of a logic “1” are stored in the negative threshold voltage memory cells or differently in the positive threshold voltage memory cells. By the allocation in this way, a half or more of the memory cells M1 to M8 in the memory block 111 have the negative threshold voltage.

#This will be explained in further detail with reference to FIG. 2. An example of FIG. 2 shows the case where there are 8 memory cells in the memory block 111, in which the numbers of a logic “1” and a logic “0” of 8 memory cells, the threshold voltages of the memory cells corresponding to a logic “1” and a logic “0”, and the threshold voltage of the bit checking translator are listed. For instance, in the case of no. 3, the number of data “1” is 2; and the number of data “0” is 6. In this case, the data of a logic “0” are allocated to the memory cells having the negative threshold voltages, and the data of a logic “1” are allocated to the memory cells having the positive threshold voltages. Further, this allocation is stored by setting the bit checking transistor CT to a positive threshold voltage. Further, in the case of no. 6, the number of data “1” is 5; and the number of data “0” is 3. In this case, the data of a logic “1” are allocated to the memory cells having the negative threshold voltages, and the data of a logic “0” are allocated to the memory cells having the positive threshold voltages. Further, this allocation is stored by setting the bit checking transistor CT to a negative threshold voltage. Further, as with the case of no. 5, when the number of data “1” is the same as that of “0”, the data of a logic “1” are allocated to the memory cells having the negative threshold voltages, and the data of a logic “0” are allocated to the memory cells having the positive threshold voltages. Further, the bit checking transistor in set to the negative threshold voltage. In the construction as described above, it is possible to always obtain half or more MOS transistors in each of which electrons ere pitted from the floating gate and thereby the whose threshold voltages are negative, in the memory block 111. Accordingly, the current flowing through the memory block 111 can be increased, and further a transistor of large current driving capability can be used as the load transistor, so that it is possible to improve the data read speed.

#Further, in FIG. 2, the case where the number of the memory cells is 8 in the memory block 111 has been explained by way of example. However, without being limited to only this example, it is of course possible to determine the number of the memory cells to another number such an 16 or 32 memory cells.