US 6,785,165 B2 · Semiconductor device

Abstract

A semiconductor device including a nonvolatile memory unit and a variable logic unit mounted on a chip is configured to achieve higher speed operation at a lower voltage. The semiconductor device includes a nonvolatile memory unit comprising a plurality of rewritable nonvolatile memory cells and a variable logic unit whose logical functions are determined, according to logic constitution definition data to be loaded into storage cells thereof. A nonvolatile memory cell essentially has a split gate structure composed of a selecting MOS transistor and a memory MOS transistor and constructed such that the dielectric withstand voltage of the gate of the selecting MOS transistor is lower than that of the memory MOS transistor or the gate insulation layer of the selecting MOS transistor is thinner than that of a high-voltage-tolerant MOS transistor. Because the selecting MOS transistor has a high Gm, a sufficiently great current for reading can be obtained.

Claims16

Dependent claims

A semiconductor device including:

a nonvolatile memory unit which comprises a plurality of rewritable nonvolatile memory cells;
and
a variable logic unit whose logical functions are determined in accordance with logic constitution definition data to be loaded into a plurality of storage cells thereof,
wherein each of said nonvolatile memory cells comprises a first MOS transistor for storing data and a second MOS transistor for selecting the first MOS transistor,
wherein, in a region of impurities under a section between a gate electrode of the first MOS transistor and a gate electrode of the second MOS transistor, no electrode common for both the first and second transistors is provided, and
wherein the gate breaks down immunity voltage of the second MOS transistor is lower than that of the gate of the first MOS transistor.

3 more elements

A semiconductor device including:

a nonvolatile memory unit;
and
a variable logic unit whose logical functions are determined in accordance with logic constitution definition data to be loaded into a plurality of storage cells thereof,
wherein said nonvolatile memory unit includes a nonvolatile memory cell which comprises a first MOS transistor for storing data and a second MOS transistor for selecting the first MOS transistor in, a third MOS transistor which performs logic operation for memory action to said nonvolatile memory cell, and a forth MOS transistor which handles a voltage required for rewriting the data of said nonvolatile memory cell,
wherein, in a region of impurities under a section between a gate electrode of the first MOS transistor and a gate electrode of the second MOS transistor, no electrode common for both the first and second transistors is provided, and
wherein gate insulation layers of the second, third, and fourth MOS transistors are formed to have their physical thicknesses fulfilling constraint tL≦ts<tH where ts is the physical thickness of the gate insulation layer of the second MOS transistor, tL is the physical thickness of the gate insulation layer of the third MOS transistor, and tH is the physical thickness of the gate insulation layer of the fourth MOS transistor.

3 more elements

Dependencies are inferred from the claim text.

Semiconductor device

Life of this patent

Semiconductor device

Life of this patent

Abstract

Claims16