Test mode decoder in a flash memory

A method of operating a memory device comprising:

• receiving a reset/power-down signal at a supervoltage level in a memory device;
• receiving a write enable signal in the memory device;
• receiving a plurality of first command signals on a plurality of input data lines coupled to the memory device;
• decoding the first command signals in the memory device during a first pulse of the write enable signal;
• receiving a plurality of second command signals on the input data lines;
• decoding the second command signals in the memory device during a second pulse of the write enable signal;
• generating an test mode clock signal in the memory device if the first command signals and the second command signals are accepted to put the memory device in a test mode;
• receiving a plurality of test command signals on the input data lines;
• and
• decoding the test command signals in the memory device during a first pulse of the test mode clock signal.

A decoder circuit comprising:

• a first input coupled to a plurality of non-inverted data lines coupled to receive a plurality of command signals representing a command;
• a second input coupled to a plurality of inverted data lines coupled to receive inverted command signals that are an inverse of the command signals;
• a plurality of sub-circuits to decode the command, and to generate a decoded signal representing the command, each sub-circuit comprising:
• a first n-channel transistor, seven middle n-channel transistors, and a last n-channel transistor coupled in series, a source/drain diffusion region of the first n-channel transistor being coupled to a ground voltage reference, a control gate of the first n-channel transistor being coupled to receive a clock signal, and a source/drain diffusion region of the last n-channel transistor being coupled to an input of a latch circuit;
• a p-channel transistor having a source diffusion region coupled to a voltage source, a control gate coupled to the ground voltage reference, and a drain diffusion region coupled to the input of the latch circuit;
• and
• wherein
• a control gate of each of the middle n-channel transistors and a control gate of the last n-channel transistor are each respectively coupled to one of the non-inverted data lines or to one of the inverted data lines to receive one of the command signals or one of the inverted command signals such that a unique pattern of command signals will switch on all of the middle transistors and the last transistor while a pulse of the clock signal switches on the first n-channel transistor to couple the middle n-channel transistors and the last n-channel transistor to the ground voltage reference;
• and
• the latch circuit is coupled to latch the decoded signal when the first n-channel transistor, the middle n-channel transistors, and the last n-channel transistor are all switched on.

A method of decoding comprising:

• receiving a plurality of command signals to be non-inverted command signals;
• inverting the command signals to generate a plurality of inverted command signals that are an inverse of the non-inverted command signals;
• coupling a first reference voltage through a p-channel transistor to a line comprising a plurality of source/drain diffusion regions of a first n-channel transistor, seven middle n-channel transistors, and a last n-channel transistor coupled in series, each source/drain diffusion region of each middle n-channel transistor being coupled to a source/drain diffusion region of an adjacent n-channel transistor;
• coupling a clock signal to a control gate of the first n-channel transistor having a source/drain diffusion region coupled to a second reference voltage;
• for each of the middle n-channel transistors and the last n-channel transistor:
• coupling a selected one of the non-inverted command signals or the corresponding inverted command signal to a control gate of the n-channel transistor such that a unique pattern of command signals will switch on all of the middle n-channel transistors and the last n-channel transistor while a pulse of the clock signal switches on the first n-channel transistor to couple the n-channel transistors in the line to the second reference voltage;
• and
• latching a decoded signal when the n-channel transistors in the line are switched on and coupled to the second reference voltage to indicate that the command signals have been decoded.