High voltage regulator for low voltage integrated circuit processes

A voltage regulator circuit, comprising:

• a voltage reduction circuit coupled to an external input;
• a back bias control circuit coupled to the voltage reduction circuit;
• and
• a voltage regulation circuit coupled to the voltage reduction circuit.

A back bias control circuit, comprising:

• one or more serially coupled input resistors, wherein each input resistor is formed in an isolation well and wherein a first input resistor is coupled to an external voltage input;
• one or more serially coupled output resistors, wherein, each output resistor is formed in an isolation well and a final output resistor is coupled to a lower power rail;
• and
• a schmitt trigger coupled to a final input resistor of the one or more serially coupled input resistors and to a first output resistor of the one or more serially coupled output resistors, wherein the schmitt trigger selectively enables and disables at a predetermined voltage threshold value of the external voltage input.

A Flash memory device, comprising:

• a memory array containing a plurality of floating gate memory cells;
• an address interface coupled to a row address decoder and a column address decoder;
• a control circuit coupled to the memory array and the address interface;
• and
• a voltage regulator circuit, wherein the voltage regulator circuit is coupled an external voltage input and the memory array and is adapted to provide a programming current and a programming voltage when the Flash memory device operates in fast programming mode and wherein the voltage regulator circuit comprises:
• a voltage reduction circuit;
• a back bias control circuit;
• and
• a voltage regulation circuit.

A system, comprising:

• a processor;
• and
• a Flash memory device coupled to the processor, wherein the Flash memory device comprises:
• a memory array containing a plurality of floating gate memory cells;
• an address interface coupled to a row address decoder and a column address decoder;
• a control circuit coupled to the memory array and the address interface;
• and
• a voltage regulator circuit, wherein the voltage regulator circuit is coupled an external voltage input and the memory array and is adapted to provide a programming current and a programming voltage when the Flash memory device operates in fast programming mode and wherein the voltage regulator circuit comprises:
• a voltage reduction circuit;
• a back bias control circuit;
• and
• a voltage regulation circuit.

An integrated circuit, comprising:

• a voltage reduction circuit coupled to an external input;
• a back bias control circuit coupled to the voltage reduction circuit;
• and
• a voltage regulation circuit coupled to the voltage reduction circuit.

A method of operating a voltage reduction circuit, comprising:

• receiving an external voltage at an integrated circuit;
• applying an optimal back bias voltage to a voltage reduction circuit that is formed in an isolation well when the external voltage reaches a predetermined threshold value;
• and
• reducing the external voltage with the voltage reduction circuit.