Device that makes it possible to selectively use nonvolatile memory as RAM or ROM
AssigneeRenesas Technology Corp.
InventorHidenori Nagashima
Life of this patent
Estimating the term…
Abstract
Nonvolatile memory cells are arranged at crossing points of bit-lines and word-lines. A mode signal indicates whether the nonvolatile memory cells are to be used as a RAM or as a ROM. When the nonvolatile memory cells are to be used as RAM, current is allowed to flow through the bit-lines in one specific direction, current is allowed to flow through the word-lines and the direction of the current flowing through the word-lines is adjusted to write data in the nonvolatile memory cells. When the nonvolatile memory cells are to be used as ROM, no current is allowed to flow through the bit-lines or the word-lines so that data can not be written in the nonvolatile memory cells.
Claims19
A memory write control device that controls writing of bit information in a plurality of nonvolatile memory cells, each one of the nonvolatile memory cells located at a crossing point of a plurality of bit-lines and a plurality of word-lines arranged in a matrix form, by controlling a direction of a current supplied to each of the word-lines, the memory write control device comprising:
- a current supply control unit that receives a current generated by a current source and a mode signal indicating the memory cells are used as one of a RAM and a ROM, and outputs the received current in accordance with the mode signal;
- a first current direction control unit that supplies the current output by the current supply control unit to each of the bit-lines in a predetermined direction;
- and
- a second current direction control unit that supplies the current output by the current supply control unit to the word-lines and controls a direction of the current supplied to each of the word-lines.
A memory write control device that controls writing of bit information in a plurality of nonvolatile memory cells, each one of the nonvolatile memory cells located at a crossing point of a plurality of bit-lines and a plurality of word-lines arranged in a matrix form, by controlling a direction of a current supplied to each of the word-lines, the memory write control device comprising:
- a current supply control unit that supplies a current generated by a current source to each of the bit-lines and word-lines in a predetermined direction, in accordance with a trigger signal indicating a data erase;
- a first current direction control unit that supplies the current generated by the current source to each of the bit-lines in a predetermined direction, in accordance with the trigger signal;
- and
- a second current direction control unit that supplies the current generated by the current source to the word-lines and controls the direction of the current supplied to each of the word-lines, in accordance with the trigger signal.
A memory write control device that controls writing of bit information in a plurality of nonvolatile memory cells, each one of the nonvolatile memory cells located at a crossing point of a plurality of bit-lines and a plurality of word-lines arranged in a matrix form, by controlling a direction of a current supplied to each of the word-lines, the memory write control device comprising:
- a first current supply control unit that receives a current supplied by a current source, and a mode signal indicating the memory cells are used as one of a ROM and a RAM, and performs one of operations in accordance with the mode signal, the operations that are outputting the received current, not outputting the received current, and supplying the received current in a predetermined direction to each of the word-lines;
- a second current supply control unit that receives the current supplied by the current source and the mode signal, and performs one of operations in accordance with the mode signal, the operations that are outputting the received current, not outputting the received current, and supplying the received current to each of the bit-lines in a predetermined direction;
- a third current supply control unit that supplies the current supplied by the current source to each of the bit-lines and word-lines in a predetermined direction, in accordance with a trigger signal indicating a data erase;
- a first current direction control unit that supplies the current output by the first current supply control unit to each of the bit-lines in a predetermined direction, in accordance with the mode signal;
- and
- a second current direction control unit that supplies the current output by the second current supply control unit to the word-lines and controls the direction of the current supplied to each of the word-lines, in accordance with the mode signal.
A magnetic memory comprising:
- a bit line;
- a word line which crosses the bit line, and which has a first node and a second node;
- a magnetic memory cell located at a crossing point of the bit line and the word line;
- a first current path which is connected to the first mode, and which includes a first ROM control circuit and a first write circuit;
- and
- a second current path which is connected to the second node, and which includes a second ROM control circuit and a second write circuit, wherein
- the first ROM control circuit supplies a first specific current, when receiving an MRAM mode signal, to the first write circuit, and does not supply the first specific current, when receiving a ROM normal mode signal, to the first write circuit,
- the first write circuit passes the first specific current supplied, when receiving a first writing signal that indicates a first memory state, to the word line so that the first specific current flows from the first node to the second node,
- the second ROM control circuit supplies a second specific current, when receiving a MRAM mode signal, to the second write circuit, and does not supply the second specific current, when receiving a ROM normal mode signal, to the first write circuit, and
- the second write circuit passes the second specific current supplied, when receiving a second writing signal that indicates a second memory state, to the word line so that the second specific current flows from the second node to the first node.
A magnetic memory comprising:
- a bit line;
- a word line which crosses the bit line, and which has a first node and a second node;
- a magnetic memory cell located at a crossing point of the bit line and the word line;
- a first current path which is connected to the first node, which includes a first write circuit;
- and
- a second current path which is connected to the second node, and which includes a second write circuit, wherein
- the first write circuit supplies a first specific current, when receiving one of a first writing signal that indicates a first memory state and a reset signal that indicates initialization of the magnetic memory cell, to the word line so that the first specific current flows from the first node to the second node, and
- the second write circuit supplies a second specific current, when receiving a second writing signal that indicates a second memory state, to the word line so that the second specific current flows from the second node to the first node.
A magnetic memory comprising:
- a bit line;
- a word line which crosses the bit line, and which has a first node and a second node;
- a magnetic memory cell located at a crossing point of the bit line and the word line;
- a first current path which is connected to the first node, and which includes a first ROM control circuit and a first write circuit;
- and
- a second current path which is connected to the second node, and which includes a second ROM control circuit and a second write circuit, wherein
- the first ROM control circuit supplies a first specific current, when receiving an MRAM mode signal, to the first write circuit and does note supply the first specific current, when receiving a ROM normal mode signal, to the first write circuit,
- the first write circuit passes the first specific current supplied, when receiving one of a first writing signal that indicates a first memory state and a reset signal that indicates initialization of the magnetic memory cell, to the word line so that the first specific current flows from the first node to the second node,
- the second ROM control circuit supplies a second specific current, when receiving an MRAM mode signal, to the second write circuit, and does not supply the second specific current, when receiving a ROM normal mode signal, to the first write circuit, and
- the second write circuit passes the second specific current supplied, when receiving a second writing signal that indicates a second memory state, to the word line so that the second specific current flows from the second node to the first node.
Dependencies are inferred from the claim text.