US 6,785,157 B2 · Semiconductor memory device having a memory cell structure of reduced occupying area

Abstract

Conductive lines constituting word lines of memory cells and conductive lines constituting memory cell plate electrodes are formed in the same interconnecting layer in a memory device including a plurality of memory cells each including a capacitor for storing data in an electrical charge form. By forming the capacitors of the memory cells into a planar capacitor configuration, a step due to the capacitors is removed. Thus, a dynamic semiconductor memory device can be formed through CMOS process, and a dynamic semiconductor memory device suitable for merging with logic is achieved. Data of 1 bit is stored by two memory cells, and data can be reliably stored even if the capacitance value of the memory cell is reduced due to the planar type capacitor.

Claims20

Dependent claims

A semiconductor memory device, comprising:

a plurality of memory cells arranged in row and columns, each of said memory cells including a capacitor including a cell plate electrode and a storage electrode arranged facing to said cell plate electrode, for accumulating electric charges corresponding to storage data;
a plurality of word lines arranged corresponding to the rows of memory cells and each connecting to the memory cells in a corresponding row, said word lines being formed in a same interconnection layer as the cell plate electrodes;
a plurality of bit lines arranged corresponding to the columns of memory cells and each connecting to the memory cells on a corresponding column, the bit lines being arranged in pairs;
and
row selecting circuitry for selecting an addressed word line out of the word lines in accordance with an address signal, the memory cells being arranged such that data in selected memory cells on an addressed row are simultaneously read out onto bit lines in a pair by a selected word line.

2 more elements

A semiconductor memory device, comprising:

a plurality of memory cells, arranged in rows and columns, each including a capacitor including a cell plate electrode for receiving a reference voltage and a storage electrode for accumulating electric charges corresponding to storage data;
a plurality of word lines, arranged corresponding to the rows of the memory cells, each connecting to the memory cells on a corresponding row, each word line comprising an interconnection line formed in a first lower interconnection layer different from and below a second interconnection layer of the cell plate electrode, and arranged adjacently to said cell plate electrode;
and
a plurality of bit lines, arranged corresponding to the columns of memory cells, each connecting to the memory cells on a corresponding column, the bit lines being formed above the word lines and the cell plate electrode, the memory cells being arranged such that two memory cells aligned in a column direction shares a contact to a corresponding bit, the memory cells adjacent in a row direction are simultaneously connected to corresponding bit lines, and the memory cells connected to a pair of bit lines adjacent to each other constitute a unit for storing 1-bit data.

1 more element

Dependencies are inferred from the claim text.

Semiconductor memory device having a memory cell structure of reduced occupying area

Life of this patent

Semiconductor memory device having a memory cell structure of reduced occupying area

Life of this patent

Abstract

Claims20