Hierarchical pixel readout multiplexer with switched capacitors for cancelling buffer offsets

A method of operating a hierarchical readout circuit connected to a plurality of lines at which individual voltages are developed, said readout circuit comprising a plurality of first capacitors respectively interposed in a plurality of lines, a plurality of first buffers respectively connected to the outputs of said first capacitors, a second buffer, and a second capacitor connected between a selected one of said first buffers and the second buffer, the method comprising the steps of:

• a) before said individual voltages appear at said lines, briefly biasing the inputs and the outputs of said first capacitors simultaneously and briefly biasing the output of said second capacitor;
• b) allowing said individual voltages to briefly appear at said lines and briefly biasing the output of said second capacitor;
• c) selecting one of said first buffers, briefly biasing the output of a corresponding one of said first capacitors and coupling the output of the selected first buffer to said second capacitor;
• and
• d) repeating steps (a) to (c).

A method of operating a hierarchical readout circuit connected to a plurality of lines at which individual voltages are developed, said readout circuit comprising a plurality of first capacitors respectively interposed in a plurality of lines, a plurality of first buffers respectively connected to the outputs of said first capacitors, a second buffer, and a second capacitor connected between a selected one of said first buffers and the second buffer, the method comprising the steps of:

• a) before said individual voltages appear at said lines, briefly biasing the inputs and the outputs of said first capacitors simultaneously and briefly biasing the output of said second capacitor;
• b) allowing said individual voltages to continuously appear at said lines and briefly biasing the output of said second capacitor;
• c) selecting one of said first buffers, briefly biasing the output of a corresponding one of said first capacitors and coupling the output of the selected first buffer to said second capacitor;
• and
• d) repeating step (c).

A solid-state imaging device comprising:

• a matrix array of photodiodes;
• a plurality of switching transistors respectively connected to said photodiodes for coupling voltages respectively developed by a row of said photodiodes to a plurality of lines;
• a plurality of first capacitors respectively interposed in said plurality of lines;
• a plurality of first buffers respectively connected to the outputs of said first capacitors;
• scanning circuitry for selectively coupling one of the outputs of the first buffers to a circuit node;
• a second buffer for producing an output signal;
• a second capacitor connected between the circuit node and the second buffer;
• and
• bias control circuitry for controlling potentials at the inputs and the outputs of said first capacitors and a potential at the output of said second capacitor so that the output signal of the second buffer contains a differential voltage between a bias voltage and each of said individual voltages, wherein said control circuitry is configured to simultaneously bias inputs and outputs of said first capacitors before said individual voltages appear at said lines, selectively bias the output of each of the first capacitors again in the presence of said individual voltages at said lines, and periodically bias the output of the second capacitor before each of said first capacitors is selectively biased again.